summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2008-05-22Changes to make flashrom compile (and work) on FreeBSD.Andriy Gapon
This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21This is a simple patch which allows payloads to be placed in memory inMyles Watson
the range of 0xf0000-0x100000, where the Coreboot tables live in v2. As long as the payload doesn't need the tables, it seems harmless, so why not just print a warning? This allows v2 to load "legacybios" without having to have a separate loader. Signed-off-by: Myles Watson <mylesgw@gmail.com> It'll be fine for testing and doesn't really break anything that did work before... Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21Add KEY_ESC (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21Myles reported SST49LF080A status -> TESTED_PREWPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20coreinfo: Use the ESC key to exit the payloadJordan Crouse
Enable the ESC key to close coreinfo - useful if you are using a chooser and want to return to it. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20coreinfo: Fix the subwindow refresh based on the libpayload changesJordan Crouse
Changes to libpayload to fix subwindows broke coreinfo. This fixes it, and improves performance by eliminating the entire screen refresh every second. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20libpayload: Add an exec() and i386_do_exec() functionJordan Crouse
Add functions for libpayload to execute other payloads in memory, and have those functions return cleanly. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20libpayload: Add larfptr functionJordan Crouse
Add a function to get a pointer to the start of a LAR entry. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20libpayload: Fix curses subwindowsJordan Crouse
This fixes subwindows in curses so that they draw and refresh correctly. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20Add post-RAM init code for the Fintek F71805F Super I/O.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Richard Stellingwerff <remenic@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-19Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.Aaron Lwe
This also contains various improvements of the CN700 code in svn. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).Uwe Hermann
Tested on hardware: Intel Northbridge: 8086:1a30 (i845) Intel Southbridge: 8086:2440 (ICH2) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17flashrom: Support Pm49FL004/2 Block Locking RegistersNikolay Petukhov
The PMC chips understand both LPC and FWH flash commands. When in FWH mode (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block Locking Registers by default lock the flash chip for write and erase - in addition to any chipset write protection. This patch adds unlock operations before Pm49FL004/2 write and erase, and it includes an svn mv pm49fl004.c pm49fl00x.c Thanks go to Nikolay for this patch. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16I looked at the datasheet and erase_sector_39sf020() is totally andCarl-Daniel Hailfinger
completely wrong. It was a straight cut'n'paste from SST 28SF040 code and the person doing the cut'n'paste didn't even bother to check the data sheet. The SST 39SF020 is completely incompatible with the 28SF040. No need for replacement. According to the data sheet, standard JEDEC commands will work and we have those commands in the tree already. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Doesn't have to be executable (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to allMarc Jones
the possible IRQs generated by the SIO. This included IRQ 7 as the default parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards that were setting it to prevent the conflict and crash when the MFGPT driver loads. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16New Target and initial support for the Thomson IP1000.Joseph Smith
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16ICH8 and ICH9 have an almost identical SPI interface, only the locationCarl-Daniel Hailfinger
of the SPIBAR differs. Add ICH8 support to the ICH9 code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Add support for the Atmel AT25DF321 SPI flash (tested).Dominik Geyer
Change ST M25P32 status to tested. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Add support for SPI chips on ICH9. This is done by using the generic SPIDominik Geyer
interface. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Enable IT8716F LPC-to-SPI write cycle translation in flashrom if theCarl-Daniel Hailfinger
IT8716F decodes any address to the attached SPI ROM. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Print detailed status register information for SST25VF series flash.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it ↵Joseph Smith
detects if the memory is already initialized, if so it issues a hard reset through the southbridge. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Lots of new SST flash chip IDs. Only a subset has been added toCarl-Daniel Hailfinger
flashchips.c, but the IDs in flash.h will make lookups easier if anybody wants to add support for them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Add support for the JEDEC RES (Read Electronic Signature and Resume fromCarl-Daniel Hailfinger
Powerdown) SPI command to flashrom to identify older SPI chips which can't handle JEDEC RDID. Since RES gives a one-byte identifier which is shared among many different vendors and even different sizes, we want to match RES as a last resort if RDID returns 0xff 0xff 0xff. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> This is a heavily reworked version of a patch by Fredrik Tolf, which was Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Some NSC Super I/Os can have their config port at 0x15c (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Cosmetics, whitespace, coding style, partially ident-aided (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14libpayload: implement wborder functionJordan Crouse
Implement the wborder function for curses to draw a box around a window. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14libpayload: Fix the putc functionJordan Crouse
Reverse rows and columns on the video putc() function, and watch printf work again. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14add ICH7-M and ICH7 DH to inteltool (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add more infrastructure for flashrom ICH9 support.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14fix license mentioning in manpage (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14trivial patch: move maintainable parts to the top and add ICH7-M DH southbridgeStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14trivial patch to fix options. Thanks to Uwe Hermann for the hint!Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add the Intel 6300ESB as known chipset to the chipset struct enables.Claus Gindhart
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Fix crash caused by division by zero for unknown flash chips.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Check the JEDEC vendor ID for correct parity. Flash chips which can beCarl-Daniel Hailfinger
detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7Stefan Reinauer
have different register meanings, so they get their own lookup tables. This is a trivial patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add lots of ATMEL SPI flash chips to flash.h.Carl-Daniel Hailfinger
Add a few flashchips already mentioned in flash.h to flashchips.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move all IT87xx specific SPI routines from spi.c to a separateCarl-Daniel Hailfinger
file it87spi.c. No behavioural changes, but greatly improved SPI abstraction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Add new revised inteltool that dumps all kinds of chipset information and ↵Stefan Reinauer
drop old gpio_dump utility. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13This is a trivial patch which fixes the tint build by removing the extraMyles Watson
typedef for time_t. The other half bumps the tint patch revision in buildrom to take advantage of it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move the SPI #defines from spi.c to spi.hCarl-Daniel Hailfinger
This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Change the SPI parts of flashrom to prepare for a merge ofCarl-Daniel Hailfinger
ICH9 SPI support. In theory, this patch has no behaviour changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OKCarl-Daniel Hailfinger
by Harald Gutmann. SST39VF040 has been confirmed to probe OK by misi e. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LFCarl-Daniel Hailfinger
series has the same IDs. Add short AMIC vendor ID to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11Fix the build when serial console support is disabled (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11Quickfix to repair 'make clean; make menuconfig' (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10Improve flashrom SPI abstraction, second step.Carl-Daniel Hailfinger
This paves the way to have a fully generic generic_spi_command without knowledge about any SPI controller. The third step would be calling SPI controller functions via a function pointer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10flashrom: Rename generic_spi_*() functions to spi_*()Peter Stuge
This is a very early step toward cleaning up SPI code in flashrom. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 09:57:14 +0000