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2015-07-23glados: Fix the write protect GPIO exported in ACPIDuncan Laurie
Update the write protect GPIO reported in ACPI to be 71 which is GPP_C23. Also update the controller id to INT344B:00 which will point at the sunrisepoint device in /sys/class/gpio. BUG=chrome-os-partner:42560 BRANCH=none TEST=verify crossystem output with and without WP enabled Change-Id: I625859bd8ac371a5c0cae18697dccf216c26a8b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fc5cb6b72dacd6aefe69fe8204f4e0d209ed8a4 Original-Change-Id: I04892e75f9bfe739c44eb40e7c6a969c33e157ca Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286842 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11035 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23glados: Add SPD manufacturer and part numberDuncan Laurie
The FSP memory info hob does not return this data so we need to supply it from the SPD included with the mainboard. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=execute "mosys memory spd print all" on glados Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258 Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286877 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23intel: common: Let mainboard supplement FSP memory infoDuncan Laurie
Since the FSP memory info HOB does not return all the data that we need about a DIMM add a weak function that will allow the mainboard to supplement the generated memory_info structure. Ideally this would not be necessary but until FSP returns the module part number we need this. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=run "mosys memory spd print all" on glados Change-Id: Ic6d0ee0a31d23efcf7e7d7f18a74e944e09e7b46 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34ad7f1906ba526e52d38d5a6bce7b88b83f0c13 Original-Change-Id: I8509c5c627c1605894473fdea567e7f7ede08cf9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286876 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11033 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23intel/common: Add SMBIOS memory widthLee Leahy
Add SMBIOS symbols to define the memory width. Update the Intel common code to display the memory width and provide the memory width to SMBIOS. Also display the memory frequency, size and bus width in decimal. BRANCH=none BUG=None TEST=None Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846 Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282115 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23glados: Set the write protect GPIODuncan Laurie
The write protect gpio is not added to the gpio map so the structure is not valid for vboot to consume. BUG=chrome-os-partner:42560 BRANCH=none TEST=build and boot on glados, check basic crossytem output CQ-DEPEND=CL:286911 Change-Id: I228d75049b919449072e395699c822203a08f1c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d15438c4bf56d92189f2f501a62b55b5d00ba461 Original-Change-Id: I3290c4b96e1cc675c618a983915b778f11175020 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286930 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11031 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23skylake: sanitize pcr header for ACPI and assemblerAaron Durbin
Remove the C types and functions from PCR so that pcr.h can be included from assembly and ACPI. While in there make the PCR reg caclulation using a C function and place the P2SB (PCH_PCR_BASE_ADDRESS) address in iomap.h. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I9cde178bcdbf49327ef7892393fc277f6c74f34b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fdf5c77ecfa0ca8d3c45604d15b9dec9a6e85193 Original-Change-Id: I5996efaa9869f8f412e4d45c13f30233384a38b2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286901 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23skylake: provide more clarity for PCR accessAaron Durbin
The current primary to sideband (P2SB) code for private configuration register (PCR) access weren't very clear with the naming or reasoning for some of the code. Provide more verbiage surrounding this interface. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247 Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286900 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23cyan/strago: disable Ambient Light Sensor deviceJagadish Krishnamoorthy
No devices are connected to i2c4 bus on both strago and cyan board. Hence disabling the ALS platform data. This will fix the i2c4 timeout issue and also help in boot time optimization. Removed unused macros. BUG=None BRANCH=chrome-os-partner:41934 TEST=After booting to kernel, i2c4 timeout error message should not appear in dmesg. Change-Id: Ib7ab4c95b0830a8d4e53c6c0ee919649ad1ed354 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c52b64037b46016fe01f1d55c4c58f7684eb778 Original-Change-Id: Ia7acdcef67a2f2837866f56aa0426a02ee05db46 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283608 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23intel/strago: BCRD2: Enable Realtek Audio codec on I2C4Jenny TC
In BCRD2, RTEK audio codec is connected to I2C4. Create a RTEK device entry on I2C4 to enable Audio on BCRD2. In BCRD1, RTEK device is connected to I2C2. Having two devices with same HID breaks the Audio on BCRD2 even if I2C2.RTEK._STA returns 0. The Audio codec driver in kernel is hard coded to use first instance of the device (:00). When two devices are present with same HID, first device gets an instance number :00 even though _STA returns 0. Second device which is on I2C4 and POR for BCRD2 assigned with instance number :01. The device with :01 is not getting enabled since the Audio codec driver supports only :00. This need a proper fix in kernel which is in the pipeline. Audio on non BCRD2 platforms on Strago build would be disabled since RTEK device is not present on I2C2. BRANCH=None BUG=None TEST=Build and boot the system Change-Id: Ia97d011c951275e6179c8b79a22c496b8169356b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d71a41ee703e6f60299b9e31a408af2ca06d8e24 Original-Change-Id: I4b032e930e46da77474f8f5969e95f9560b3e905 Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285193 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: http://review.coreboot.org/11003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23vboot: set software write protect flagDaisuke Nojiri
TEST=built for samus and veyron_jerry Change-Id: I7173f46d2ed2e323bff227a484c32c4bb6f6c828 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/11028 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-22amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machinesJonathan A. Kollasch
Moves the K8 CPU_ADDR_BITS definition from socket to model. Previously socket_F was not setting CPU_ADDR_BITS correctly. Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs. Most if not all K8-based chips support 40-bit physical addresses, with possible exception of IA32-only K8-based Athlon XP-M chips. Probably irrelevant, unless your machine has enough memory (at least 60 to 64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from src/cpu/x86/Kconfig. Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10963 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-22riscv: Link in libgccPatrick Georgi
The new toolchain depends on it. Change-Id: I9070925eeb3f63a6c31e7474ffb9cba15884703d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-22winent/mb6047: move power_on_after_fail out of RTC century byteJonathan A. Kollasch
Change-Id: I3cf6a579f4e62a59828e81aa63c3a1a020a15ea6 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10906 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-22lib/hexdump: Add xxd hintLee Leahy
For people new to Linux, add the xxd hint to compare output with output from Linux. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ia46aeed056b12abbadf8205b044944385d9410e1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-22intel raminit: rewrite timB high adjust calculationPatrick Rudolph
Found while doing code review. Simplify the code by using a loop for positive and negative phase adjustments. Change-Id: I0980443d0d2815bccef969709fddecc07d61a788 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10890 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-22intel raminit: support two DIMMs per channelPatrick Rudolph
Issue observed: Two memory DIMMs are placed in the same channel, but only one shows up. The SPD is read and printed, but the first DIMM isn't recognized any more. Due to an existing but unconfigured memory DIMM the timB test failed. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: The channel's rankmap was overwritten by the second slot's rankmap. Problem solution: Logical OR the channel's rankmap with every slot's rankmap. Final testing result: The DIMM is recognized and can be properly configured and used. The timB test doesn't fail any more. Change-Id: I17a205ff4d344c13d9ddfe71aaae2f3cef047665 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10960 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-22crossgcc: Support /bin/sh pointing to dashPatrick Georgi
It doesn't know "source", but wants the older "." instead Change-Id: Iafa61b1d2ffc9c737ab67a417c62417593b69374 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10974 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21cpu: port amd/agesa to 64bitStefan Reinauer
Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10579 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-21Port Fam14 northbridge code to 64bitStefan Reinauer
Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10583 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-21intel/fsp_baytrail: Support Baytrail FSP Gold4 releaseYork Yang
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-21t132: Correct dma_busy functionTom Warren
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA operation is complete. However, in case of ONCE mode, use STA_BSY bit to determine if DMA operation on the channel is complete. This change was propogated from T210, commit ID fe48f094 BUG=None BRANCH=None TEST=Ryu/Rush build OK. Change-Id: I13073cc12ed0a6390d55b00c725d1cc7d0797e23 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aab62d5148b57fd1e05c1e838eafe8fdee431ef8 Original-Change-Id: I7388e9fd73d591de50962aaefc5ab902f560fc6f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286468 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11017 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21t210: Add tegra_lp0_resume codeYen Lin
BUG=chrome-os-partner:40741 BRANCH=None TEST=tested on Smaug; able to suspend/resume Change-Id: I3e796bee4b1bedfd4cce0a37549108d5271658a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 207ca26cb2c157c0dcf476c4d4973b4d4ec67cc7 Original-Change-Id: I8565d4cf1632d6d3023aa55b2bff824a092f2c3b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277025 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11018 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-21libpayload: lz4: Add output overrun check to incompressible caseJulius Werner
The LZ4 decompressor currently doesn't check for output overruns before writing data in the case where a block had been incompressible (and included verbatim in the compression stream). This is extremely unlikely with the default 4MB blocks, but still a nice thing to fix. We'll still output as much data as we can before returning an error to support partial decompression use cases. This matches the behavior already in place for normal, LZ4-compressed blocks where the decompression function is already (supposed to be) doing complete bounds checking (although it is not guaranteed to output all valid bytes before aborting on an output overrun, and you should try to provide a few dozen bytes of extra buffer space beyond the parts you're interested in on partial decompression). BRANCH=None BUG=chrome-os-partner:32184 TEST=None Change-Id: I5e40c8cec8947ec0ec8f6d8c8fa2574cfb4dc958 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 636985334c9b3b93a12d4066d2829f1f999c9315 Original-Change-Id: Iecf44650aade60b9fa1b13e57da752fb482a3f3f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286240 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21t210: Correct device MMIO rangeJimmy Zhang
Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and can not be accessed by Bootloader. Issue found in CL: 283104 is captured by this patch. BUG=None BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware Here are memory mapping table before and after this CL for evt2 board: Before: Mapping address range [0000000000000000:0000000040000000) as cacheable | read-write | secure | device Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal After: Mapping address range [0000000001000000:0000000040000000) as cacheable | read-write | secure | device Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2 Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285260 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11015 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21arm64: Set LOG_LEVEL=0 for BL31 if coreboot does not use serialFurquan Shaikh
Even if DEBUG=0, BL31 puts NOTICE(..) messages on serial console. Set LOG_LEVEL=0 if coreboot does not use serial. BUG=None BRANCH=None TEST=Compiles successfully and no console output from bl31 for production images. Change-Id: Ie77bcac3e2a0d314545b6811327c413536c77fb9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8e3bcbf6249c80850a87dd66f34d3ff36158641 Original-Change-Id: I1415a3816cd2fa9dd05bcbd36ac0abc3f2759960 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286150 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11014 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-21google/cyan: Configure EC_IN_RW signal as gpio inputHannah Williams
BUG=chrome-os-partner:42881 BRANCH=None TEST=Using ctrl-d in recovery mode to switch to dev mode works. Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5 Original-Reviewed-on: https://chromium-review.googlesource.com/286612 Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11013 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21mec: Correct the access mode for short payloadsJagadish Krishnamoorthy
If the Host Command payload is less than 4 bytes and is word aligned then the payload was not transferred at all. EC reads the old packet and CRC mismatch occurs. In this issue, the HC command packet consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD as payload encountered the same problem as above. Hence select byte access mode for shorter payloads. BRANCH=None BUG=chrome-os-partner:42396 TEST=System should boot after chromeos-firmwareupdate Change-Id: I22bdb739108d31b592c20247be69c198d617d359 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286537 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21skylake: add global reset cause registers to power stateAaron Durbin
Log the global reset causes in the power state structure. While working in there pack the struct and use width-specific types as this struct crosses the romstate <-> ramstage boundary. Lastly, remove hsio version as it wasn't being written or read. After global reset induced: PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 00000000 00000000 00000000 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: d8010200 00003808 GBLRST_CAUSE: 00000000 00040004 Previous Sleep State: S0 BUG=None BRANCH=None TEST=Induced global reset on glados using ETR3 register and write to cf9. Change-Id: I97b93de336e74c0e02199241376e74340612f0a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47 Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286640 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11011 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21intel/cyan: Fix crossystem "wpsw_cur" statusHannah Williams
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community were in two ranges: 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error. The original offset was 0x16 whereas it should be 0x13 BUG=chrome-os-partner:42798 BRANCH=None TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286534 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11010 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Kunimitsu: Add comment and separate routinesLee Leahy
Document the lid open state and separate the routines with a single blank line. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: I244f20c03bc7530ad8d140fba41dd97c12c079e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 57313253fdef3f2d3f0e16b8ab8aa91202d45b16 Original-Change-Id: I7b3bd9cf16e915d214eb2de0017a8d91a934b112 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286267 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/11009 Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Kunimitsu: Remove address from copyright noticeLee Leahy
Remove the address from the copyright notices. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: Ibe8196841d9e76c9ee3a3dbae802ecc63dc7904c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cc12d2658324a375d02748098f0a2f4b5d1b5615 Original-Change-Id: I81a71e4ad9b8a66ad0e9a93cbeb512d90eb35906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286266 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/11008 Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Tested-by: build bot (Jenkins)
2015-07-21skylake: take into account deep s3 in power failure checkAaron Durbin
If a resume from S3 is occuring one needs to take into account deep S3 in order to check the proper power failure bits. When deep S3 is enabled the suspend well will be turned off. Therefore don't look for that bit when determining a power failure. BUG=chrome-os-partner:42847 BRANCH=None TEST=Suspend and resumed with deep s3 enabled and disabled. Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2 Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286271 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: read out and report full width of gen_pmcon registersAaron Durbin
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and save the full 32 bits for completeness. BUG=chrome-os-partner:42847 BRANCH=None TEST=Built and booted. Noted output on terminal. Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0 Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286270 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Cyan: Tune charger current limit in performance states table.li feng
Charger performance states table defines charger current limit for each p state. Modify charger current control values for SANYO battery used in Cyan. BUG=None BRANCH=None TEST=System is charging battery, in shell window, issue command "echo 0 > /sys/class/thermal/cooling_device4/cur_state", "echo 1 > /sys/class/thermal/cooling_device4/cur_state", "echo 2 > /sys/class/thermal/cooling_device4/cur_state", "echo 3 > /sys/class/thermal/cooling_device4/cur_state", or "echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC console show different charging current value. Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09 Original-Signed-off-by: li feng <li1.feng@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285605 Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: http://review.coreboot.org/11004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Glados: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21kunimitsu: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART 1 and 2 in devicetree for kunimitsu boards. UART1 are disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu. Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627 Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284825 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Sklrvp: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART 1 and 2 in devicetree for sklrvp boards. UART1 is disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3. Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21intel/skylake: support 32bit uart8250_mem driver in romstageNaveen Krishna Chatradhi
This patch adds 32bit uart8250_mem functionality in romstage console for arch/x86. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp; verified romstage logs on RVP3 board. Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765 Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21console: Add UART8250MEM 32bit supportNaveen Krishna Chatradhi
This patch adds UART8250MEM_32 feature flag to support UART8250 compatible with 32bit access in memory mapped mode. [pg: rebuilt to reuse the existing UART8250 8bit access driver which reduces code duplication.] Change-Id: I310e70dfab81dcca575e9931e0ccf93af70efa40 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c3b2c628b854e8334540ff5158c2587dbfabf95 Original-Change-Id: I07ee256f25e48480372af9a9255bf487c331e51d Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21google/glados: add new boardPatrick Georgi
Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel/common: remove printk in pre_console_init()rsatapat
printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Initialize GPIOs for UART2rsatapat
FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Only support UART2 as debug port, clean up the restNaveen Krishna Chatradhi
On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21cyan/strago: Disable wwanJagadish Krishnamoorthy
Disabling the wwan gpio line since wwan is not used. BRANCH=none BUG=none TEST=wwan should not connect to network on cyan/strago. Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285304 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Braswell: Remove GOP from normal boot mode.Abhay Kumar
Removing GOP initialization in normal mode since we don't need to show splash screen in normal mode. GOP will get initialized in dev and recovery mode. BRANCH=none BUG=None TEST=Splash screen will come only in dev or recovery mode. Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5 Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d Original-Signed-off-by: Abhay <abhay.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: re-enable PCIe L1 sub statesAaron Durbin
All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21Sklrvp: Select PCIEXP_L1_SUB_STATE config symbolNaveen Krishna Chatradhi
This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe. BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled" Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-14 16:24:29 +0000