Age | Commit message (Collapse) | Author |
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Noticed-by: Uwe Hermann
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialization. It can reduce KBC init time by up to 400 ms on
real hardware, and by a minute or so on AMD simnow.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Trivial change.
Reported-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This redirects that output to the console and implements a basic
keyboard stub.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Fix a typo, too.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to using ram, so something like the appended is perhaps more
appropriate. Confirmed to work on hw.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialization. Not all payloads require it and some keyboards take a
long time to init.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ready (PSON gating). Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Removing the code preloading reduces the boot time.
Preload code is enabled when doing CARTEST (not exposed
to Kconfig given that it's a pure debugging measure)
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and SB600.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.
Move RAMBASE to the default of 1MB for the affected boards
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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0xc0000-0xfffff, have coreboot qemu support enable the memory range at
startup.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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platform specific value. Before that, we can set it manually if the boards
need to run in a higher frequency, which has been tested on Tilapia.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME
I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and 5. They're not found if only function 0 is checked. So if a device
exists at all, try all its functions. usb_controller_initialize() will
silently skip all device classes != 0C03.
(changed to continue to use 32bit accesses -pg)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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While we're at it, improve DESTDIR handling
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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boards were specified in Kconfig, and abuild depended on that. Since that rev
it has only built qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to those files that actually need it. This significantly reduces the number of
dependencies, so it's no longer extremely ugly to specify them manually (see
the src/pc80/Makefile.inc portion)
Also, drop the AMD DBM690T work around for the issue.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the Intel ICH10 Family Datasheet.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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would rather not have mainboard settings like sio_gp1x_config in the
device tree anyway. So found a nice united home for both in Kconfig,
where users can change them without having to mess around in the C code.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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be used in write levelization training.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This should be unproblematic, as there are other boards with the same "socket"
that work with CAR already. Tests are highly appreciated though!
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Kconfigs from within the choice/endchoice block. This makes it possible to
define user visible board specific options. Moved all vendor names and PCI
ids to the vendors' Kconfigs. Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if". Sorted boards
(sort -d), cleaned whitespace.
This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used. It it simply needed to have something to attach
the boards' "select" statements to.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/mainboard/Kconfig | 8 ++
src/mainboard/lanner/Kconfig | 8 ++
src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++
src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++
src/mainboard/lanner/em8510/chip.h | 23 +++++++
src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++
src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++
src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++
src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++
src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++
10 files changed, 418 insertions(+), 0 deletions(-)
create mode 100644 src/mainboard/lanner/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
create mode 100644 src/mainboard/lanner/em8510/chip.h
create mode 100644 src/mainboard/lanner/em8510/cmos.layout
create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
create mode 100644 src/mainboard/lanner/em8510/mainboard.c
create mode 100644 src/mainboard/lanner/em8510/romstage.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/northbridge/intel/i855/Kconfig | 30 +
src/northbridge/intel/i855/i855.h | 76 +++
src/northbridge/intel/i855/northbridge.c | 21 +
src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++-----
src/northbridge/intel/i855/raminit.h | 14 +-
5 files changed, 1002 insertions(+), 175 deletions(-)
create mode 100644 src/northbridge/intel/i855/i855.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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