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2018-04-11arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer
RISC-V does not have the kind of I/O space that x86 has. Other architectures tend to leave out these definitions as well. Change-Id: I7328dae1f1fa4ef8772750244a0b11a3fa5aa88f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-11drivers/aspeed/Kconfig: Select HAVE_VGA_TEXT_FRAMEBUFFERDaniel Gröber
This allows VGA output in SeaBIOS to be enabled using the SEABIOS_VGA_COREBOOT Kconfig option. Currently, it’s impossible to select the VGA text frame buffer in the Kconfig menu. I'm not sure why this wasn't enabled in the first place, but SeaVGABIOS seems to work just fine with this patch. Tested on KCMA-D8. Change-Id: Ic924a12fbe89940b5f26d211eb8de6cab0be767a Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/25554 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/intel/dg43gt/devicetree.cb: Use tabs over spacesElyes HAOUAS
Change-Id: I5d18dfea0b0a33995de805219bda3a73892e5fde Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-11soc/intel: Remove superfluous pointers variablesArthur Heymans
Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common: Configure all possible GFX DSM memory reserve rangeSubrata Banik
Intel internal graphics preallocated memory size should be selected from below lists as per Intel FSP UPD header: 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB This patch ensures that coreboot can report the same preallocated memory range for intel grapics during memory layout calculation. Note: Today all existing SoCs(except Cannonlake) are supported under intel common code block design may not need to use any other values than 0x0-0x05 for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for early SoC samples and validation requirement. This code block to justify all differnet possible ranges that FSP may support for a platform. TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB and coreboot could able to calculate GFX DSM range accordingly. Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11drivers/intel/wifi: Add support for Harrison Peak (HrP)Subrata Banik
Move all Intel WIFI PCI ids into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration. Change-Id: Ia2d15f3f4a68887521ddbb1b99daf9d98cfa5c8b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10mb/google/octopus: Capitalize MB part nameJustin TerAvest
This is for consistency with other platforms. BUG=b:77494826 BRANCH=None TEST=Sucessfully rebooted, saw updated name in SMBIOS Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25591 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10soc/intel/apollolake: fix SPI input clock speedAaron Durbin
On APL and GLK the i2c blocks use 133MHz input clock, but the SPI blocks use a 100MHz input clock. Fix this so that the proper target frequencies can be hit on the SPI controllers. BUG=b:75306520 Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-10soc/intel/cannonlake: Set Cannonlake I2C clockLijian Zhao
Correct Cannonlake I2C clock frequency to 133Mhz that will match the silicon, Cannonlake have I2C clock force to 133Mhz. BUG=b:75306520 Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25610 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10soc/intel/common: prepare for lpss clock splitAaron Durbin
Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10soc/amd/stoneyridege: Create AP jump structureRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, create infrastructure to pass a pointer to the AP cores, so they can jump directly to romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/amd: Add "halt this AP" callback to romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, callback function AGESA_HALT_THIS_AP must be available at romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: I0992b2de5856881c19191ec4f637168727686524 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25527 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mainboard: Make OemCustomize.c available at romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25528 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10Documentation: Fix a bunch of typosJonathan Neuschäfer
Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10Documentation: Rename submodules.txt to submodules.mdJonathan Neuschäfer
This will help static site generators that can turn Markdown into HTML but can't easily turn plain text into HTML. Change-Id: Iabdbbecd0badddbca2221c6164b254ca163555ad Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-10Documentation: Convert abi-data-consumption.txt to MarkdownJonathan Neuschäfer
This will help static site generators that can turn Markdown into HTML but can't easily turn plain text into HTML. Change-Id: Id186db140503f3c2759d579b18476fff021988c8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-10util/board_status/to-wiki: Remove link to xivo's git treeJonathan Neuschäfer
coreboot doesn't support any Xivo boards, and their tree has been only available as a tarball for a while. Let's remove this link from the Supported Motherboards page's preamble. It's still listed on https://www.coreboot.org/Supported_Motherboards/old. Change-Id: I50e7bec02e803b62563f21384d857f1b37904dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10util/board_status/to-wiki: s/corebootv4/coreboot/Jonathan Neuschäfer
corebootv4 vs. just coreboot has lost its significance. Version 4.0 has been released in February 2010. Change-Id: Ic2a35739e53fea411efc8691f1ba7db85ba0c764 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10mb/google/poppy/atlas: Fix SPD index in commentJonathan Neuschäfer
Fixes: ba49c09b2f ("mb/google/poppy: Add variant for Atlas") Change-Id: I9c5c10abf8129ff61b97312a70ed4749606a3090 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10cpu/amd/microcode/microcode.c: Remove unneeded whitespaceElyes HAOUAS
Change-Id: Ib6f73dc0b0d11f6b66b7dbdd33cd6785359191ab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-10mb/google/poppy: Disable rear camera for all vayne skuAmanda Huang
Since there are two cameras on Nami and only one camera on Vayne. We need to disable rear camera on all Vayne sku. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera shown on Vayne Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09cpu/x86/mtrr: Use single code path with/without holesNico Huber
Now that calc_var_mtrrs_with_hole() always chooses the optimal allocation, there is no need for calc_var_mtrrs_without_hole() any more. Drop it and all the logic to decide which one to call. Tests performed compared to "upstream" (before "cpu/x86/mtrr: Optimize hole carving strategy") on a Lenovo/X200s with 48MiB GFX stolen memory. 2GiB total RAM: 3 MTRRs saved MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007ac00000 size 0x7ab40000 type 6 0x000000007ac00000 - 0x00000000d0000000 size 0x55400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/8 > 6. MTRR: default type WB/UC MTRR counts: 4/7. MTRR: WB selected as default type. MTRR: 0 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 4GiB total RAM: no MTRRs saved but slightly more accurate alignment MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017c000000 size 0x7c000000 type 6 upstream: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f00000000 type 6 patched: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f80000000 type 6 8GiB total RAM: possible savings but WB still beats UC MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000027c000000 size 0x17c000000 type 6 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/11 > 6. MTRR: default type WB/UC MTRR counts: 4/10. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/7 > 6. MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 Change-Id: Iedf7dfad61d6baac91973062e2688ad866f05afd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09cpu/x86/mtrr: Optimize hole carving strategyNico Huber
For WB ranges with unaligned end, we try to align the range up and carve a hole out of it which might reduce MTRR usage. Instead of trying an arbitrary alignment, we try all and choose an optimal one. Also, restructure the cases when we try to find a hole. Which leads us to the following three: 1. WB range is last in address space: Aligning up, up to the next power of 2, may gain us something. 2. The next range is of type UC: We may align up, up to the _end_ of the next range. If there is a gap between the current and the next range, it would have been covered by the default type UC anyway. 3. The next range is not of type UC: We may align up, up to the _base_ of the next range. This is the end of the gap, if there is one. Change-Id: Iefb064ce8c4f293490a19dd46054b966c63bde44 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09mb/google/octopus: Enable EC wakeShaunak Saha
This patch sets the wake for EC to proper gpios. BUG=77605178 TEST=Test that lidopen wakes up the system from S3. Change-Id: Icbf30007403191005396027e74b9b6fb7319e006 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25539 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/apollolake: Fix GPIO group to GPE mapping for GLKHannah Williams
BUG=b:77605178 TEST=Tested EC wake sources Change-Id: Id879b3e91d4c0794662cf3d8204bd077117db23c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-04-09soc/intel/apollolake: enable MONITOR/MWAIT for GLKCole Nelson
MONITOR/MWAIT had an irremediable hardware bug for Apollolake. This has been fixed for GLK. Therefore, make MONITOR/MWAIT based C-states the default for GLK and disable IO-Redirection based C-states used for Apollolake. Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state residencies with and without load. Tested for S0ix entry and exit using: "echo freeze > /sys/power/state" and "suspend_stress_test -c 500". BUG=b:77639897 Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Signed-off-by: Cole Nelson <colex.nelson@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/19718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/common: Add funtion to modify PAT & NXE bitNaresh G Solanki
Add function to modify NXE bit & PAT. BUG=None BRANCH=None TEST=Make sure build for Glkrvp is successful. Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25480 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus/variants/baseboard: Add DPTF parametersSumeet Pawnikar
This patch adds the DPTF parameters for Octopus baseboard. These parameters are copied from reef/coral as initial reference values. BUG=None BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621 Reviewed-on: https://review.coreboot.org/25339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09ACPI S3: Drop too early resume backupKyösti Mälkki
No longer needed as low memory backup is implemented as part of the ramstage loader, when the actual requirement of the ramstage to load is known. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15477 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-09lib/lzmadecode: Add block around `UpdateBit1()`Paul Menzel
Fix the error below. ``` src/lib/lzmadecode.c: In function 'LzmaDecode': src/lib/lzmadecode.c:77:2: error: macro expands to multiple statements \ [-Werror=multistatement-macros] Range -= bound; \ ^~~~~ src/lib/lzmadecode.c:300:7: note: in expansion of macro 'UpdateBit1' UpdateBit1(prob); ^~~~~~~~~~ src/lib/lzmadecode.c:299:8: note: some parts of macro expansion are not \ guarded by this 'else' clause } else ^~~~ cc1: all warnings being treated as errors ``` The macro is defined as below. #define UpdateBit1(p) \ Range -= bound; \ Code -= bound; \ *(p) -= (*(p)) >> kNumMoveBits Found-by: gcc-8 (Debian 8-20180402-1) 8.0.1 20180402 (experimental) [trunk revision 259004] Fixes: 35af5c47 (src/lib: Fix spacing) Change-Id: Ife0688541e23c05e26e429a6d8caee7e2d425b1b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09amd/stoneyridge: Add GNB IOAPIC initMarc Jones
Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09crossgcc/Makefile: don't allow to call buildgcc in parallelAlexander Couzens
Change-Id: If296414f8cb3bc87862cdc20f3d3acc1a3f78556 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/21229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09device/dram/ddr2.c: Add methods to compute to identify dramArthur Heymans
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till 98. Compute a crc16 over that data to provide a solid way to check DIMM identify. Reuse the crc16 function from ddr3.c to do this. Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-09ioapic: extend definition name to avoid collisionMarc Jones
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other EN/DISABLE definition. Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25540 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common locationNaresh G Solanki
Move flush_l1d_l2 function to common location within the SoC. BUG=None: BRANCH=None TEST= Build for glkrvp. Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09vboot: Add support for reading GBB flagsFurquan Shaikh
This change adds basic support for reading flags from GBB header located in "GBB" section on SPI flash. Change-Id: I35ecb5ba964511379baa4e9f458ba2e8c6b74b4e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09util/lint: Generate json output from checkpatch outputNaresh G Solanki
checkpatch_json.py processes the output of checkpatch.pl & generates json format output of comments. This json format output can be used to post comment on particular CL using gerrit. BUG=None BRANCH=None TEST= Run following commands: 1. Capture output of checkpatch.pl to file say checkpatch.txt nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl --no-signoff -q - | tee checkpatch.txt 2. Generate json format file for the output. util/lint/checkpatch_json.py checkpatch.txt comment.json 3. Post the comment.json using gerrit ssh coreboot.org gerrit review -j "<CL number>,<patchset number>" < comment.json Change-Id: I2471792796ab8e7d9855a6559fc731345ebd1525 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/23429 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09console: Expose vsnprintfDavid Hendricks
It's a standard function. Change-Id: I039cce2dfc4e168804eb7d12b76a29af712ac7a1 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06docker/coreboot-sdk: Add device-tree-compilerPatrick Rudolph
Add dtc to Dockerimage for Jenkins. Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25525 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/lenovo/w520: Add ThinkPad W520 supportNico Rikken
Tested and working: * 4 RAM-slots * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events * USB 3.0 * SD-card reader * Native graphics (LCD panel) * Harddisk in Ultrabay * SeaBIOS payloads ** Debian Live ** Debian testing 4.14.0-3-amd64 * GRUB ** Debian Live ** Debian testing 4.14.0-3-amd64 Not working: * Displayport and VGA output (requires VGA option ROM and ACPI switch call) Not tested: * Intel VGA option ROM * ACPI events related to ultrabay * Smart card reader * Docking station Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/23564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-06mainboard: Add ASUS Maximus IV GENE-ZTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with kernel 4.9. This code is based on the output of autoport. Working: - S3 suspend/resume - USB - Gigabit Ethernet - integrated graphics - PCIe - SATA - eSATA - PS/2 port (only a mouse has been tested) - hardware monitor - onboard audio - front panel audio - native raminit (2 x 4GB + 2 x 8GB, DDR3-1333) - native graphics init with libgfxinit - EHCI debug. The debug port is the port closest to the HDMI port. - flashrom, using the internal programmer. Tested with coreboot, untested with the vendor firmware. - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been tested with values different from the default. Untested: - VGA BIOS for graphics init - PCIe graphics - S/PDIF audio Not working: - "clear CMOS" button The CPUTIN sensor on the Super I/O is not connected. The PECI agent is likely connected instead to give CPU temperature readings. However, there does not appear to be enough information in the publicly available datasheets to fully set up the PECI agent. As a result, there is currently no accurate, automatic fan control via the Super I/O. Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/24971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD HeadersNg Kin Wai
Header files based on FSP 7.0.25.34 BUG=none BRANCH=none TEST=built coreboot without build error. Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com> Reviewed-on: https://review.coreboot.org/25335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-04-06mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel ECNaresh G Solanki
When building with Intel EC selected, unselect Chrome EC specific options i.e., LID switch to prevent build error. BUG=None BRANCH=None TEST=Build with Intel EC selected, Build should be successful. Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25479 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06fsp_broadwell_de: Provide valid address and size for DCACHE rangeWerner Zeh
On Broadwell-DE the FSP sets up DCACHE in the early call. The address does not match the default FSP 1.0 address defined in src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range is used in pre-ramstage stages. This patch provides the matching DCACHE_RAM_BASE value among with a suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation. The include order of Kconfig files makes sure that the Kconfig file in the soc directory is sourced first and the defined values will override the ones in src/drivers/intel/fsp1_0/Kconfig. Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06fsp_broadwell_de: Provide valid ACPI path names for domain and LPCWerner Zeh
Provide ACPI path names for PCI domain and LPC device so that generated ACPI tables have valid device paths. Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06mb/google/octopus: Edge trigger cr50 interruptJustin TerAvest
Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06sb/intel/common/firmware: Allow CONFIG_USE_ME_CLEANER on Kaby LakeNicola Corna
Some users have reported a successful boot with me_cleaner on Kaby Lake with OEM firmware: https://github.com/corna/me_cleaner/issues/3 It should work as well on coreboot. Change-Id: Ifc47f19deee5c39ca27b427c9406da7f6e3e9f15 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25507 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06util/me_cleaner: Update to v1.2Nicola Corna
Changelog: * Add support for the HAP/AltMeDisable bit * Add support for selective partition removal * Fix the ME permission removal on gen. 3 * Add public key match * Print the compressed size of the Huffman modules on gen. 2 * Wipe the ME6 Ignition firmware images * Fix the removal of the last partition on ME6 * Various region size fixes * Add manpage * Add setup.py * Print the value of the HAP/AltMeDisable bit The output image should be identical, except for the platforms affected by bugs (ME 6.x, but it's not supported by coreboot and ME 11.x with the -d option, but it's not being used in our build process). Overall, nothing should change when it's used with the CONFIG_USE_ME_CLEANER option. Tested on a Lenovo X220 and Sapphire Pure Platinum H61. Change-Id: I3d5e0d9af0a36cc7476a964cf753914c2f3df9d2 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:00:33 +0000