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2012-11-05Overhaul speedstep codeNico Huber
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05Fix some indentation flaws and break very long linesNico Huber
Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02remove enable_cache() of 3 mainboardsSiyuan Wang
Because enable cache is added at the end of disable_cache_as_ram, ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc ) enable_cache() should be removed. The 3 mainboards are: amd parmer, amd thatcher and tyan s8226 Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1669 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-02Persimmon: disable the unconnected Full-Speed USB portDave Frodin
Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
add this code according to src/include/cpu/x86/cache.h ,line 92, functin enable_cache() Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1662 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02Correct FSB reading in speedstep ACPINico Huber
We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02crossgcc: build expat and python in silenceIdwer Vollering
Don't let expat and/or python show the compile process on stdout. Instead direct this output to crossgcc-build.log. Fix the logfile path for python. Change-Id: I431dabf6955d7eef3e54c96d0fb11b92d1cee96d Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
Unfortunately the reference tool chain was updated without ever even testing it on an abuild run. This broke a number of ports. This change gets coreboot at least compiling again for all supported systems. Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1670 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-01add .gitreviewDavid Hendricks
This adds a .gitreview file for use with the git-review tool. More information is available at the URL below: https://labsconsole.wikimedia.org/wiki/Git-review Change-Id: I723d78bf7dd81c5756e684d5b166210246fe2daf Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1665 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-30Add support for socket LGA775Stefan Tauner
Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1581 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-30Fix ExecuteFinalHltInstruction function in f15h family codeKostr
Current ExecuteFinalHltInstruction function doesn't work well. (at least in configuration Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU)) System reboots when trying to halt core 2,4,6,8 or 10 (OS6234WKTCGGU is 12 core processor) Based on this information, i think that code doesn't really work with f15 compute unit (CU) system. Replacing ExecuteFinalHltInstruction function with analogous function from f15tn family code fix this problem. Both functions written from the same cahalt.asm file, but f15tn version seems more completed Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf Signed-off-by: Kostr <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/1569 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-30AMD SB800: PCIE slots on PersimmonZheng Bao
Enable the PCIE bridge which is connected to the PCIE slot. Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1098 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-10-29Fix reading of number of interrupts for IO-APICsNico Huber
The number read from the io-apic register represents the index of the highest interrupt redirection entry, i.e. the number of interrupts minus one. Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1624 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-29Hide all _ROM_RUN Kconfig options if the payload is SeaBIOSPeter Stuge
The options are shown regardless of payload if CONFIG_EXPERT is set. Change-Id: I12c81ce41a0e300e852481424eadc83f281863bf Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1638 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-29Run option ROMs in coreboot by default only if the payload is not SeaBIOSPeter Stuge
Change-Id: I29fb86ff3a3187b720ce5ef246c4eeee696ab5cd Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-29Clarify that _ROM_RUN Kconfig options control if ROMs are run by corebootPeter Stuge
Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-28IEI PM-LX2-800-R10: Added preliminary mainboard supportRicardo Martins
Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050662496936266123&id=09034367569861123956 Support for the IT8888 PCI to ISA bridge will be added in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1152 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27inteltool: Add output of 64bit registers in PMBASENico Huber
Output values of 64bit registers and fix settings for GPE0_EN for ICH9/10. Change-Id: I8ca6b32500331707670972b38466345f581844cd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1625 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27libpayload: New AHCI, ATA and ATAPI driversNico Huber
This adds a new interface for storage devices. A driver for ATA and ATAPI drives on AHCI host controllers comes along. The interface is very simple and was designed to match FILO's needs. It consists of three functions: void storage_initialize(void); Initializes controllers. Should be called once at startup. storage_poll_t storage_probe(size_t dev_num); with typedef enum { POLL_NO_DEVICE = -2, POLL_ERROR = -1, POLL_NO_MEDIUM = 0, POLL_MEDIUM_PRESENT = 1, } storage_poll_t; Looks for a drive with number dev_num (drives are counted from zero) and polls for a medium in the drive if appropriate. int storage_read_blocks512(size_t dev_num, u64 start, size_t count, unsigned char *buf); Reads count blocks of 512 bytes from block start of drive dev_num into buf. Change-Id: I1c85796b7f8e379ff3817a61b1837636b57e182b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27Take care of NULL chip_ops->nameKyösti Mälkki
Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27Reorder entries in .gitignoreStefan Tauner
Change-Id: I7fcf190ef92b06b857d8b85c3d27da9cdee071b1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1633 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27Add docs and util files to .gitignoreStefan Tauner
This adds... - generated documentation files - all kinds of stuff in the util subdirectories Change-Id: I47ab6d239aae725f54413f03424f40002ac5a275 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1572 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27crossgcc: update to Python 2.7.3Idwer Vollering
Change-Id: I9db10e8c7dcd693cc4ab935c587da02dd7eb2bc5 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1621 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27crossgcc: update to expat 2.1.0Idwer Vollering
Change-Id: Id0b736d402b33138e27b18c74e5ed8ffab0bcccb Signed-off-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1620 Tested-by: build bot (Jenkins)
2012-10-26iwave/iWRainbowG6: use 16bit access for a register which is not 32bit alignedSebastian Andrzej Siewior
The PCI registers should be accessed aligned and 0x62 is not 32bit aligned therefore this patch changes it to a 16bit access. Change-Id: I00725a4569f471eedb061834f626911b42e734fb Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1631 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
Without this, the output of "Setting up ACPI…" continues right after the output of stepping. Change-Id: I2ad7cc3e55884ff509600b01274258b8e8250981 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1632 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-10-26iwave/iWRainbowG6: remove USE_DCACHE_RAMSebastian Andrzej Siewior
This is not available as a config option anymore. Change-Id: Icac173d62928423a08671321ec21d4af82c5cded Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1630 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c but it is not written there. The size of memory is written in src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for "Setting up TOM"). Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1629 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
The GGC register which contains the size of memory that is used for GPU is in PCI device 2,0 and not 0,0. It is set to to 4MiB in src/mainboard/iwave/iWRainbowG6/romstage.c. Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1628 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
Without this, the hightables are placed just before the end of memory. However we might have the GPU memory located at the exact same spot, that is in the last 4 MiB. So without this patch, this area won't remain marked as "CONFIGURATION TABLES" within coreboot's memory table but becomes "RESERVED" because it is part of the PCI(2,0) device. Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1627 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-10-26crossgcc: update mingw w32api's download URLIdwer Vollering
Correct the download URL of mingw's w32api. Change-Id: I98fb43c121399c23f6693ade5cd3b42bc9463724 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1619 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-26buildgcc: redirect error output to /dev/nullZheng Bao
Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1548 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-26crossgcc: update to mingwrt 3.20-2Idwer Vollering
This patch updates crossgcc to download and compile mingwrt 3.20-2 Change-Id: Ic5ed2df4c3643e469a62c51643d3fc756eb3e615 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1617 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-10-25crossgcc: update to binutils 2.23Idwer Vollering
This patch updates crossgcc to download and compile binutils 2.23 Change-Id: I75a24ce6fb9f6ac7ae53671314c410b9b0d80aa8 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1615 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to MPC 1.0.1Idwer Vollering
This patch updates crossgcc to download and compile MPC 1.0.1 Change-Id: I7a2a21afc8c26e4fb7b6553c7fd98cc054d01570 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1614 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to MPFR 3.1.1Idwer Vollering
This patch updates crossgcc to download and compile MPFR 3.1.1 Change-Id: I6c479db5d6d632dcc2201c3771b43e2b663877e1 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1613 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to GDB 7.5Idwer Vollering
This patch updates crossgcc to download and build GDB 7.5 Change-Id: I38fc3591396f072ead399b22f516ec765480ea40 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1612 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to gcc 4.7.2Idwer Vollering
Update crossgcc to use gcc 4.7.2. This requires a minor change to util/crossgcc/buildgcc as well. Tested on hardware with asus/p2b and lenovo/x60. Change-Id: Ia3921844670ca99741e5715def14dd969f305ab7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1609 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: fix compilation of acpicaIdwer Vollering
Compilation of acpica-20120420 is broken (and old, but I'll take care of that in a future patch), let's fix that ("Building IASL 20120420 ... failed"). Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1607 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-24Trinity: Initialize the pointer prior to using itZheng Bao
Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1606 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-23kconfig: Some terms or curses libraries treat backspace as 0x08Zheng Bao
Change-Id: Ie4e4a2f0d68643a8f46d24ee7bd1b953e9fe14a5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1605 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-22build: build coreboot on mingw.Zheng Bao
regex, pdcurses, wsock(for itohl) are seperated libraries. mmap and unmmap are ported from git. Issues: 1. The length of command line is limited. That makes the Thather can not be built because too many obj.o need to be built. Change-Id: I1d60ec5c7720c1e712e246c4cd12e4b718fed05f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22cbfstool: Add -mno-ms-bitfields on (mingw)Zheng Bao
The default gcc on mingw will process the __attribute__ ((packed)) in a different way other than non-win system. Change-Id: Iac9f4476c922472d0b447f1c3ef60e8e13bd902f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1603 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22Makefile: No need to mkdir when distcleanZheng Bao
make distclean causes error on mingw: ------- rm: cannot lstat `build/util': Permission denied make: *** [distclean] Error 1 ------- Guess, When the distclean is made by multi-process, the mkdir in the Makefile will execute when build is removed. That causes conflicts. Change-Id: Ia41ecc5d1db2fa9d3328c81ac1d33fa94779492d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1602 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22gitconfig: Create .git/hooks before copying files.Zheng Bao
Change-Id: Id5564bf7a12b3ea9a5e60bd9522466157ace8c65 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1601 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22change conflicted typedef in src/vendorcode/amd/agesa/f15/Porting.hSiyuan Wang
src/vendorcode/amd/agesa/f15/Porting.h has some conflicted typedef with src/include/cpu/amd/common/cbtypes.h. These conflicted defines can lead to errors. Change-Id: Idad0794018bf0bd0e4e52a5aa062a12766d56c8e Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1592 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-19inteltool: improve the libpci test in the MakefileStefan Tauner
Use the verbatim variable method to define and export test code and the actual libpci test from flashrom. This improves readability and will work with stricter compiler (settings). Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1575 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-19inteltool: add support for 946GZ and 946PLStefan Tauner
Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1576 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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