summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-01-08arch/x86/Kconfig: Fix spelling of *successful*Paul Menzel
Change-Id: If0da91cf94aa12fe7b8670f6b181e443e3446aa1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30745 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08arch/x86: Link walkcbfs.S instead of including itArthur Heymans
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the romstage. This is useful for cbfs access in pre-CAR environments. Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08cpu/intel/car/bootblock.c: Report BIST failuresArthur Heymans
The result is saved in a static variable and is reported when the console is initialised. Change-Id: I5f0f9edce68634adfe4a77a0d2c0bf3d7cd4e78e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCKArthur Heymans
Add common C entry points that hook to platform-specific bootblock code. Change-Id: I8eac974864f255811e8708997a8014a45a5c09ee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki
Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08arch/x86: Unify bootblock MMX register usageKyösti Mälkki
Have same usage of registers with romcc bootblock and C_ENVIRONMENT_BOOTBLOCK. Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-08sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans
This removes the need to synchronize the devicetree and the romstage writing to FD. Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30244 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6Arthur Heymans
The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetreeArthur Heymans
The devicetree was synced incorrectly with respect to the function disable register set in romstage. Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30711 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08soc/intel/icelake: Increase bootblock sizeSubrata Banik
This patch fixes icelake build brokenness due to bootblock size issue. Increase the bootblock size to 48K to match skylake. With UART enabled we are very near the 32K limit, and with upcoming changes to add USB devices in devicetree for a icelake board it is over the current 32K limit. BUG=b:122485106 TEST=Able to build dragonegg Change-Id: I66706e66ac1bce677fe11022d0eef44b9efc2e76 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-01-08Documentation/releases: Note the disappearance of device_tPatrick Georgi
That was truly a huge task. Change-Id: Ifd79aaf005bf39744bd4fd930ba2441f966ec0b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08Documentation: Add 4.10 release notes templatePatrick Georgi
Change-Id: Ibb7aab2367c379bbf7ab93a41ce06095916d0f95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08amdfam10 boards: Fix regression on dev_find_slot() removalKyösti Mälkki
For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are getting manipulated during HyperTransport enumeration. This workaround reverts back to old dev_find_slot() with its bad semantics. Change-Id: I19745c3070c12e562ffab2f0243c9d91dd051c72 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-07nb/intel/gm45: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27016 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07Documentation/gerrit: Update parts about WIP and draft commitsPatrick Georgi
Gerrit dropped the "draft" concept and replaced it with private commits and work-in-progress commits, options that can be used independently from each other. Change-Id: I6abe267c2091c750fc234057be3a4e62adb59c4c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-07mb/google/hatch: Enable touch panel supportMaulik V Vaghela
Following changes are done to enable touch screen support on hatch 1. Enable I2C1 device at 400Khz at 3.3V 2. Configure GPIO for touch screen 3. Add ACPI entry for ELAN touch panel 4. update GPIO table with not connected GPIO pins for panel BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-07intel/lynxpoint: Fix spellingKyösti Mälkki
Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-07src/mb/asus/p5qpl-am/romstage.c: Fix commentAngel Pons
Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30705 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07usbdebug: Sanity check PCI EHCI locationKyösti Mälkki
If requested EHCI function is not on bus 0, we would need to open MMIO windows and configuration register space for the connected upstream PCI bridge for it to work. We don't plan to do so. Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-07usbdebug: Probe for gadget only onceKyösti Mälkki
The first stage attempting to initialise usbdebug gadget will leave it marked as non-present if none is detected. This allows further stages to bypass usbdebug init sequence. Change-Id: I1491d7fab3c89f210fb03b32481f697bc7a1d1e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-07usbdebug: Initialize the HW once in CAR stagesArthur Heymans
The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-07crossgcc: Update Python to version 3.7.2Elyes HAOUAS
Change-Id: Ie0b3d31ba116314308d4fcc36a19587370fff7cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30560 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07sb/intel/fsp_rangeley: Fix typo in GPIO LevelElyes HAOUAS
Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian
2019-01-07sb/intel/bd82x6x: Fix typo in GPIO LevelArthur Heymans
Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-07mb/google/poppy/variant/rammus: enable USB acpimarxwang
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:119899987 TEST=build and flash to rammus, log into rammus and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Signed-off-by: marxwang <marx.wang@intel.com> Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b Reviewed-on: https://review.coreboot.org/c/30607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Correct I2C bus clock for touchpadLijian Zhao
Elan touchpad require connected i2c clock to be running at 400Khz, with the modification can get 404Khz speed from Arcada EVT platform. BUG=b:119628524 TEST=Build and boot up on Arcada platform, measure the i2c clock is around 400Khz. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 Reviewed-on: https://review.coreboot.org/c/30653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Modify ELAN Touchpad i2c bus clkJohn Su
Modify ELAN touchpad bus i2c clk from 466Khz to 400Khz. BUG=b:119628524 BRANCH=master TEST=measure ELAN Touchpad CLK Change-Id: Ia8433c6ef320cea9a0145db4ba440d67ccd0f41e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30588 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07src: Use "foo **bar" instead of "foo ** bar"Elyes HAOUAS
Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-01-07src: Move constant to the right side of comparisonElyes HAOUAS
Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-07soc/intel: Standardize names of common MSRsElyes HAOUAS
Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-06util/ifdtool: Fix regions_collide() checkNico Huber
The old version was unnecessarily complex and allowed one region to include the other. Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30673 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06soc/intel: Drop pmc_get_mainboard_power_failure_state_choice()Nico Huber
It's not needed anymore. Change-Id: I273acb2bf1675dc947927e3e6d2ebb78aa94518a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-06Kconfig: Unify power-after-failure optionsNico Huber
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06mb/google/slippy: Add a VBT for all variantsArthur Heymans
The vbt was extracted from the option rom found on stock images. The vbt.bin is the same across all variants. The VBT has a modified BDB block 43, the 'Backlight info block' such that the inverter type for the panel in use is set to 2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE). This only seems to matter on Windows, as without it changing the backlight duty cycle does not work. Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30487 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06superio/*: Link early initialization into bootblockArthur Heymans
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. It is likely unnecessary to do this in verstage. This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM. Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06mb/google/fizz: enable eist (enhanced speedstep)Matt DeVillier
Without eist enabled, fizz's CPU clocks are locked at the base frequency, and don't scale up or down. This prevents fizz from idling properly and turbo boost from functioning, so enable it (as is done for all other KBL boards) Test: build/boot google/fizz, ensure CPU clocks scale as expected Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.cAngel Pons
This is done for consistency purposes. Also fix a small formatting issue in a function. Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06usbdebug: Refactor init callsKyösti Mälkki
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06device: Use pcidev_path_behind()Kyösti Mälkki
Change-Id: Iac16f9412d0e6aac908d873c61a4de3935e5318a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26518 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-05cpu/intel/common: improve debug outputMatt DeVillier
currently, if the IA32_FEATURE_CONTROL lock bit is already set, VMX status isn't reported. Adjust debug output to provide more useful infomation on both VMX and lock bit statuses. Test: build/boot google/chell, observe useful output in cbmem log regardless of lock bit status. Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-05crossgcc: Update CMake to version 3.13.2Elyes HAOUAS
Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update GDB to version 8.2.1Elyes HAOUAS
Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update LLVM to 7.0.1Elyes HAOUAS
Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05util/inteltool: fix PCR init of Sunrise Point-LP devicesShaleen Jain
Fixes getting a dump of GPIO registers for these devices. Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496 Signed-off-by: Shaleen Jain <shaleen@jain.sh> Reviewed-on: https://review.coreboot.org/c/30604 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update acpica and Expat versionsElyes HAOUAS
Update: * acpica to version 20181213 changes in this version: https://acpica.org/node/163 * Expat to version 2.2.6 changes in this version: https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-04mb/*/chromeos.c: Fix PRE_RAM and unify styleKyösti Mälkki
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30399 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04mb/google/jecht: Rename save_chromeos_gpios functionKyösti Mälkki
We have init_bootmode_straps() defined for the same purpose. Change-Id: Ia2692d8f8986247ea4ce889d6252d3c4c8b27bc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30398 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 23:22:47 +0000