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2020-02-05pciexp: Add support for allocating PCI express hotplug resourcesJeremy Soller
This change adds support for allocating resources for PCI express hotplug bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of non-prefetchable memory, and 8 KiB of I/O space to any device with the PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which indicates hot-plugging capability. The resource allocation is configurable, please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig. In order to support the allocation of hotplugged PCI buses, a new field is added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-busses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05vendorcode/eltan/security: Switch to vb2 vboot libraryWim Vervoorn
The eltan verified_boot is using the vboot 2.1 data structures and code, as well as the fwlib21 build target, they are all deprecated. Refer to CB:37654 for more information. The verified_boot code is updated to use the vb2 structures and code and make sure only public functions are used. BUG=N/A TEST=build Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-04arch/x86/include/arch: Add SMM_TASK_STATE_SEGEugene Myers
This define is used to set up the STM SMM Descriptor table tr entry. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Iddb1f45444d03465a66a4ebb9fde5f206dc5b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-02-04soc/intel: Add get_pmbaseEugene Myers
Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04security/tpm/tss: Add ClearControl FunctionChristian Walter
Add ClearControl Function which is needed for a follow-up patch. Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-02-04mb/google/hatch: Enable Audio DSP oscillator qualification for S0ixAamir Bohra
BUG=b:139481313 Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-04soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idleAamir Bohra
With Audio DSP OSC qualification disabled from S0ix criteria. S0ix is achieved before the DSP is suspended. When driver tries to suspend DSP its already turned off. BUG=b:139481313 Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04soc/intel: Remove duplicate CPUID entrySubrata Banik
This patch removes duplicate CPUID entry between KBL and CFL. CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL CPUID (0x806EA) for CFL-D0. TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with CPUID 0x806EA. Change-Id: I078dd7860891896b512967dc8dec5dd94d069193 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-04cpu/x86: Make MP init timeout configurableJonathan Zhang
The current MP init timeout is hardcoded as 1s. To support platform with many cpus, the timeout needs to be adjusted. The number of cpus is calculated as: number of sockets * number of cores per socket * number of threads per core How long the timeout should be set to, is heuristic. It needs to be set long enough to ensure reboot stability, but not unreasonable so that real failures can be detected soon enough, especially for smaller systems. This patch sets timeout to be minimum as 1 second, while each cpu adds 0.1 second. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-02-04soc/amd: unify SMBus supportAaron Durbin
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-02-04mb/google/puff: Enable HECI communicationJamie Chen
Set HeciEnabled = 1 on puff device tree to turn on Intel ME communication interface. BUG=b:143232330 BRANCH=None TEST=Build puff and boot up OS. ran lspci and confirmed there is a HECI device. 00:16.0 Communication controller: Intel Corporation Device 02e0 Change-Id: I2debb885022ae31e395869d014a91824b5dd980c Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-02-04commonlib/cbfs.h: Correct spelling error in commentMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-04coreinfo/coreinfo.c: Correct main function signatureJacob Garber
libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-03Update vboot submodule to upstream masterJulius Werner
Updating from commit id 6ef33b99: 2019-11-22 Hung-Te Lin futility: updater: refactor: unify getting temp files for firmware images to commit id 0e97e25e: 2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was meant to be Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-02-03xcompile: Disable null pointer optimizationsJacob Garber
According to the C standard, accessing the NULL pointer (memory at address zero) is undefined behaviour, and so GCC is allowed to optimize it out. Of course, accessing this memory location is sometimes necessary, so this optimization can be disabled using -fno-delete-null-pointer-checks. This is already done in coreboot, but adding it to xcompile will also disable it for all the payloads. For example, coreinfo compiled with LTO libpayload crashes when this flag isn't set, presumably because the compiler is optimizing something out that it shouldn't. Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-03drivers/generic/gfx: Add null pointer error checkJacob Garber
acpi_device_scope() will return NULL if it is unable to find the path of the parent device. Return early if this is the case to prevent a null pointer dereference. Change-Id: I3eff1c1e3477c75c7130b52898de7d59692ba412 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1409672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38669 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-03lenovo/t440p: fix keyboard backlightIru Cai
It is found that keyboard backlight in T440p is enabled by clearing bit 3 of EC RAM 0x01. This patch sets has_keyboard_backlight in devicetree.cb and also corrects the CMOS configuration. Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Dennis Witzig <dennis@wtzg.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-02-01soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim
Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01hatch/mushu: Fix FPMCU pwr/rst gpio handlingCraig Hesling
Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants. This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling). BUG=b:148457345 TEST=None Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-01mb/google/hatch/variants/mushu: Enable dGPU BOMACO modeAmanda Huang
Configure GPP_H22 as output pin for BOMACO mode enabled. BOMACO stands for "Bus Off Memory Alive Core Off". BUG=b:146081272 TEST=emerge-mushu coreboot Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38210 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01ec/google/wilco: Set cpu id and cores to ECEric Lai
Set CPU ID and cores to EC then EC will adapt power table according to the CPU ID and number of cores. BUG=b:148126144 BRANCH=None TEST=check EC can get correct CPU id and cores. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS methodPeter Lemenkov
Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37944 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01sb/intel/common/acpi: Add more Windows versionsPeter Lemenkov
For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01util/inteltool: Add GPIO dumping capabilites for Ice Lake U systemsJohanna Schander
This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-02-01util/cbfstool/lzma: Make clang-11+'s indentation checker happyPatrick Georgi
Newest clang compilers warn about "misleading indentation", and because warnings-are-errors in our builds, that breaks the build. The lzma code base is vendored in, so we might just have to update it, but that's a bigger effort than just removing a couple of spaces (the coding style of the file is horrible, but I will only change it as much as the compilers ask for). BUG=chromium:1039526 Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-01mb/google/hatch: Modify kohaku's EC_SCI_EVENTS maskTim Wawrzynczak
Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=System shows ACPI interrupt as the wakeup IRQ, and the MKBP host event is properly processed as well. Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38654 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01ec/google/chromeec: Add new wrappers for host commandsTim Wawrzynczak
Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPSTim Wawrzynczak
The new host command provides these static capabilities of each USB-PD port: 1) Port number 2) Power role: source, sink, dual 3) Try-power role: none, sink, source 4) Data role: dfp, ufp, dual 5) Port location: these come from power_manager BUG=b:146506369 BRANCH=none TEST=compiles Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01util/docker/Makefile: Correct help outputWim Vervoorn
The help output suggests clean-docker should be used to remove the docker coreboot containers and images. The Makefile actually supports the docker-clean target. Corrected the help output to reflect the actual Makefile target. BUG=N/A TEST=build Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-01mb/lenovo/t520: Switch to overridetreePeter Lemenkov
Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37295 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01nb/intel/sandybridge: improve indexed register helper macrosFelix Held
Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-01mb/google/hatch: Override CPU flex ratioSubrata Banik
This patch overrides CPU flex ratio on hatch in order to get better boot time numbers in vboot_reference. BUG=b:142264107 TEST=Able to save ~100ms of platform boot time while running with lower cpu flex ratio (i.e. freq ~1500MHz) Without this CL 1100:finished vboot kernel verification 802,443 (148,108) With this CL 1100:finished vboot kernel verification 685,382 (46,496) Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36865 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01device/pnp_device: improve warning/error messagesFelix Held
Explicitly state that the assignment is missing in the devicetree. In the case of the warnings, the missing assignments might not be an issue. Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31cbfstool: Set deprecated _BSD_SOURCE and _SVID_SOURCE macrosJulius Werner
In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to tell glibc to enable "all the default stuff", meaning POSIX, BSD and System V interfaces. However, this macro is somewhat recent and older glibc versions (e.g. 2.12) are still occasionally in use that don't recognize it yet. For the benefits of users with these versions, let's also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which essentially achieve the same thing. We must continue to define _DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation warning. This patch should make BSD-style byteswap macros like le32toh() available on these older glibc versions. Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-01-31soc/amd/picasso: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/picasso: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/picasso: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/stoneyridge: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30soc/intel/common/systemagent: Add Kconfig guardAndrey Petrov
Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to some value which can't be overriden outside of soc/intel/common. So adding a non-SoC platform thats uses code from soc/intel/common is not possible. TEST=build test on wip platform Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2020-01-30util/lint: enforce SPDX license headers in src/superioFelix Held
Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-30util/*: more typo fixesPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find util -name '*.[ch]') Change-Id: I059071fd3a2edb41c72fc57fccbb520bd2ebb757 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30src/superio/*: Fix typosPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find src/superio -name '*.[ch]') Change-Id: I36fd8cfeffdaf81d7ac646bab7ffac3e36c77879 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30Documentation/vendorcode/eltan: Update security documentWim Vervoorn
Update the security document to reflect the current state of the coreboot implementation. Add more detail and document the change to the public vboot API. BUG=N/A TEST=build Change-Id: I228d0faae0efde70039680a981fea9a436d2384f Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/msrtool: Fix formatting issues reported by checkpatchPatrick Georgi
Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/msrtool: Fix typosPatrick Georgi
The Intel docs also call it "Scalable Bus Speed", so the typo is on us. Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/msrtool/*.c Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/cbfstool: Fix typosPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/cbfstool/*.c Change-Id: I13a27407bf2bad4b9fadcec8cdbd5889068f13cf Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/lint: Update spelling.txt from lintian data setPatrick Georgi
commit 1191c09201b43aab55333a70d056d0c355abe329 at https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides a much more comprehensive collection of misspellings, so merge it in. While at it, also sort the file for future easier merging which is the main reason that some lines appear to be removed: they're merely moved. For sorting, I adapted their make rule: make -f - sort-spelling.txt <<'EOF' .RECIPEPREFIX=% sort-%: % %csplit --prefix $<- $< '/^$$/' %LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $< %rm -f $<-0[01] EOF Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:33:24 +0000