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2020-12-31broadwell: broadwell_refcode_maine7240_bdwIru Cai
2020-12-30add PchStartUsbInitIru Cai
2020-12-29bdw refcode: use finalize_usb C codeIru Cai
2020-12-29bdw: use librem mrc and refcodeIru Cai
2020-12-28e7240_bdw: init mec5055Iru Cai
2020-12-28e7240_bdw: add SSTIru Cai
2020-12-28e7240: add 00:13.0Iru Cai
2020-12-28dell/e7240: add bdw versionIru Cai
2020-12-28mainboard: add Dell Latitude E7240Iru Cai
Based on autoport output. It boots from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2020-12-28ec: Add support for MEC5055 for Dell laptopsIru Cai
This EC support code is required to boot various Dell Latitude laptops, otherwise the laptop will shut down in a minute after being powered on. Tested on Dell Latitude E7240. Change-Id: Iee68ea52dcf0242315868a46b5e4768303e30dce Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2020-12-28an important PPI fixIru Cai
2020-12-28add fffd295dIru Cai
2020-12-28do not use mrc_printkIru Cai
2020-12-28mark mrc_printkIru Cai
2020-12-28add broadwell_mrc.asmIru Cai
2020-12-28add broadwell_refcode.asmIru Cai
2020-12-289480m_bdw: update from bdw codeIru Cai
2020-12-28[WIP] mb/hp: Add EliteBook 820 G2Iru Cai
Currently it boots to SeaBIOS. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2020-12-28[WIP] mb/hp: Add HP ProBook 640 G1Iru Cai
Generate code from autoport. It boots to Arch Linux in a USB disk from SeaBIOS payload. This board doesn't have HP Sure Start enabled, so we can use all the flash regions, and relocate the EC firmware with CB:41393. Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2020-12-28[HACK] Add soc/broadwell based hp/folio_9480m codeIru Cai
The laptop still boots with this code. Change-Id: I0d74c59ff8e8f32f49627fb7edc270887ebd5339 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2020-12-27mb/siemens/chili/base: Add SMBIOS slot descriptionsFelix Singer
Add SMBIOS slot descriptions for M.2 ports and remove duplicate comments. Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27vpd: Add vpd_get_int() functionNico Huber
Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45773 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings appear in reference code. Add them for the sake of completeness. Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
The steppings correspond to the CPUID bits 3:0, so move them to the CPU scope, and include the CPU header from files using the stepping macros. Change-Id: Idf8fba4911f98953bb909777aea57295774d8400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
Rewrite some constants to make their meaning somewhat clearer. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
Native raminit only supports 1.5V operation, but there are DIMMs which request 1.65V operation in XMP profiles. Add an option to force XMP to be used when the requested voltage isn't supported, which will run the DIMMs at 1.5V with XMP timings. Consider this to be overclocking. Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25ACPI: Allocate GNVS early in ramstageKyösti Mälkki
We need this to happen prior to SMM module loader. If there is some debugging output it's better they do not appear in the middle of CPU bringup. Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25ACPI: Fix some GNVS field commentsKyösti Mälkki
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25sb,soc/intel: Fix GNVS OperationRegionKyösti Mälkki
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000. Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25mb/google/dedede: Update galtic device treeFrankChu
Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-25soc/intel/common/gfx: rename and guard graphics_soc_init()Matt DeVillier
Rename to graphics_soc_panel_init, to more accurately convey operations performed by the function. Guard execution so we don't attempt to reconfigure the panel after FSP has already done so. This fixes FSP/GOP display init on APL/GLK, which was broken by attempting to configure the panel after FSP had already done so. Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25drivers/ipmi: Add Supermicro OEM commandsPatrick Rudolph
Add a new driver for OEM commands and select it from x11-lga1151-series. The driver communicates the BIOS version and date to the BMC using OEM commands. The command should be supported on all X11 series mainboards, but might work with older BMC, too. Tested on X11SSH-TF: The BIOS version strings are updated on boot and are visible in the BMC web UI. Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-24Documentation: Add Beaglebone Black documentationSam Lewis
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24libpayload/i8042: Add API to peek on keyboard input queueNico Huber
Change-Id: I60699e044b5bacd3f5292fed7edbf529ae133284 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47592 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24libpayload/keyboard: Add debug output to all state transitionsNico Huber
Change-Id: I643a821d4c41fc068f2bab0bd571b0a4a359f59a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24libpayload/keyboard: Hide console output by defaultNico Huber
Change-Id: I855d975a4729da34a6fa73a63dbbd12c856bdc00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24libpayload/keyboard: Implement self-testNico Huber
The keyboard self-test is required for some devices. At least one device (integrated keyboard in a ThinkPad X201) actually starts the test automatically leading to spurious output and no response for the first seconds. We wait up to 5s for the self-test result. On failure or timeout, the command will be repeated until the 30s init timer runs out. This happens all in the background of the UI polling loop. To not unnecessarily delay the boot process, we first try an oppor- tunistic initialization which skips the self-test. Change-Id: Ie07b31e74d06e116ac81e76309621eed39a19b49 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24libpayload/keyboard: Add timestamp to track time spent in a stateNico Huber
Will be used to time out in states that don't always advance. Change-Id: I28235e7638d8157cedf81fd915a41d28a1fc070b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47087 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24libpayload/keyboard: Turn init sequence into a state machineNico Huber
We'll process the init sequence as part of the polling loop. This should have several advantages: * It eases error handling, i.e. we can return to an earlier state. * We don't have to stall initialization when a keyboard takes a little longer. * Generally, these keyboards can be hot-plugged (albeit not by design). Change-Id: I9cf5cf31eb420b3994bec20e56a72d37f3d2996e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24libpayload/keyboard: Avoid races around input drainingNico Huber
Draining the keyboard's buffer is only possible when the keyboard port is enabled. We should also disable input scanning before, as the buffer could be filled again with new keystrokes otherwise. Change-Id: Ibac9c0d04880ff4a3efda5ac53da2f9731f6602c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24libpayload/keyboard: Introduce keyboard_drain_input()Nico Huber
Move the input-buffer draining into a function. It uses the low-level i8042 API directly to avoid conflicts with changes in the high-level keyboard API. Change-Id: I9427c5b8be4d59c2ee3da12d6168d34590043682 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24libpayload/keyboard: Revise keyboard_cmd() error handlingNico Huber
Even if we are careful, it's still possible that we read spurious data from the keyboard, e.g. keystrokes. Namely, when we send the reset/disable command, there is a race before the command is pro- cessed. So we should always process data from the keyboard in a loop. We break it, when an ACK (0xfa) or a NAK (0xfe) is received, and warn on unexpected data unless it might be due to the mentioned race. This also gives us the opportunity to use command-specific timeouts which we take from Linux: 1s for the keyboard self-test (as there are keyboards that perform the test before acking the command) and 200ms for all other commands. Change-Id: I60a2643a8ff4b9231c63bf970c8749c97c7d8926 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24mb/prodrive/hermes: Drop EEPROM address function parametersAngel Pons
Only one EEPROM is used to store the board settings, and its I2C address is constant. Thus, there's no need to pass its address as a parameter. In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since using it outside of eeprom.c would bypass the API's abstraction layer. Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Use already-defined SMBus macrosAngel Pons
Drop chipset register definitions in mainboard code in favor of existing definitions in a header. These definitions are not mainboard-specific. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/supermicro/x11-lga1151-series: Select DRIVERS_UART_8250IOPatrick Rudolph
Change-Id: I0251d1193bb36ae73d592a0d17f580b7edaddbf6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48853 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24mb/google/volteer/variant/lindar: Add SSD D3 cold supportKevin Chang
This patch add SSD D3 cold support for lindar. BUG=b:172405687 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD cardDavid Wu
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-243rdparty/fsp: Update submodule pointer to newest masterFelix Singer
Newest master introduces the FSP for Tiger Lake client SKUs. Change-Id: Id437faf72f1b8c5bc5310596bdab980e64614fa0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48712 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24mb/google/volteer/var/voema: Enable RTD3 for the NVMe deviceDavid Wu
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:169356808 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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