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2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
Change-Id: Ide87c45806c5e58775c77e7f780efb4cf81a70c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16014 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-04soc/apollolake: Return correct wake status in _SWSShaunak Saha
Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-04soc/intel/apollolake: Configure gpio ownershipJagadish Krishnamoorthy
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04google/reef: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: If5a6a1cb8f065a8c3a6a19d9441a21d60b39e579 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16031 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04soc/intel/skylake: Correct address of I2C5 DeviceBarnali Sarkar
This corrects the address of the I2C5 Device. The I2C Controller #5 is on PCI Bus 0: Device 25: Function 1. The ACPI Address Encoding Logic is - High word = Device #. Low word = Function #. So, I2C5 (_ADR) = 0x0019 0001. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: I4719a843260ef58cc2307e909e9ccbffea519177 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16048 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04lib/timestamp: Add timestamps to CBMEM in POSTCAR stageFurquan Shaikh
POSTCAR stage has cbmem online. So, all timestamps need to be added to cbmem timestamp region. BUG=chrome-os-partner:55848 TEST=Verified that timestamps added in postcar show up in cbmem -t. Change-Id: I64af8c1e67b107d9adb09de57c20ea728981f07c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16032 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-03lenovo/x60: Fetch 16 bits when trying to parse bit 13Patrick Georgi
I'm not sure if that's the right fix here, but assuming the bit mask is right, the inb is wrong. Change-Id: I7e33019af088780a09be12513200bec63734bf97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229556 Reviewed-on: https://review.coreboot.org/16026 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03sb/amd/sb[6|7|8]00: Initialize PICTimothy Pearson
The PIC was not initialized, leading to hangs when booting Linux as a payload. This error was hidden by both SeaBIOS and GRUB due to both payloads initializing the PIC as a matter of routine. Change-Id: I9a3b9bd831d4dafdd0bb82ea023026a10fe7efca Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16018 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-03spi/tpm: read TPM version in larger chunksVadim Bendebury
The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead, and increase the length limit to 300 bytes to accommodate longer version strings. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/16000 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03google/gale: Add more board ID variantsKan Yan
EVT1 has two board IDs. Use binary first mode of base3 encoding for board ID. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I1cac1f74207f42616111d39db5c0494b7d1a0fb2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2b16cc74c4c147315b7db345678bbaf536ab4a7b Original-Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364623 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/16030 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add code to support I2C TPM for KevinJulius Werner
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add support for Gru rev1Julius Werner
This patch adds support for the Gru rev1 board. This board differs from rev0 by no longer relying on the I2C backlight booster and requiring the same ODT SDRAM settings as newer Kevin boards. BRANCH=None BUG=chrome-os-partner:55087 TEST=None Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28 Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364624 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03payloads/coreinfo: Set KCONFIG_CONFIG valueMartin Roth
The KCONFIG_CONFIG value was previously keeping the value set by coreboot's makefile. That caused it to overwrite coreboot's .config, making the current coreinfo build and the next coreboot build fail with the curious error that you were building without the correct toolchain. Change-Id: I973b0c36e7227135a5c2d6d261e08889857aaaf1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16023 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03soc/intel/quark: Support access to CPU CR registersLee Leahy
Add support to access CR0 and CR4. TEST=Build and run on Galileo Gen2. Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03util/checklist: Place tables in proper boot orderLee Leahy
during the boot, romstage occurs before postchar which is before ramstage. Place the tables in the proper boot order when generating the final webpage. TEST=Build and run on Galileo Gen2 Change-Id: I5df3ceb797aced58fe5ea3d10d78254a27341e47 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03util/checklist: Concatinate optional list to complete listLee Leahy
Don't require that the routines in the .optional file be listed in the .complete data file. Concatinate the two files when building the complete symbol list. TEST=Build and run on Galileo Gen2 Change-Id: I596134e1a19311d357aa0d93cfb33c7ca9801e2e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16037 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03util/checklist: Process .debug files before .elf filesLee Leahy
Ensure that the output file is created by processing the .debug files before the .elf files. TEST=Build and run on Galileo Gen2 Change-Id: Ief8d774249c9d8eb313f3d10f04d7e4f2e3cf491 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03util/checklist: Add usage instructionsLee Leahy
Document how to use the checklist and how to generate the data files. TEST=Build and run on Amenia Change-Id: Idffc0683e916cbc5a984028886dc3d89a01d0595 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03mainboard/intel/galileo: Add FSP 2.0 Kconfig supportLee Leahy
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15864 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Add header files for FSP 2.0Lee Leahy
Add the FSP 2.0 header files for Quark. These files were run through the drivers/intel/fsp2_0/header_util to convert the data types so that they are compatible with the coreboot build system. TEST=Build and run on Galileo Gen2. Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15863 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Prepare for FSP2.0 supportLee Leahy
Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03soc/intel/quark: Initialize MTRRs in bootblockLee Leahy
Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs. TEST=Build and run on Galileo Gen2. Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15861 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Remove use of EDK-II macros and data typesLee Leahy
Include assert.h to use coreboot's ASSERT macro. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15858 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03fsp_broadwell_de: Add DMAR table to ACPIWerner Zeh
Create DMAR table for Broadwell-DE SoC. TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and disassembled DMAR table using iasl. The table contents are as expected and the kernel loads DMAR table without errors. Change-Id: I7933ba4f5f0539a50f2ab9a5571e502c84873ec6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15913 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-03cbfstool: Check for excessive argumentsNico Huber
Change-Id: I66de6a33b43c284198c0a0a97c5c6a10f9b96e02 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16019 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03cbfstool: Check arguments to strtoul() where appropriateNico Huber
The interface to strtoul() is a weird mess. It may or may not set errno if no conversion is done. So check for empty strings and trailing characters. Change-Id: I82373d2a0102fc89144bd12376b5ea3b10c70153 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16012 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03Makefile.inc: Strip output of `wc`Nico Huber
Apparently BSD's wc indents its output. Change-Id: I77f50a4b7d6012782f1c1b42ba20a64721c186c8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16013 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
PCI root ports with "Address Translation Service" capability can be reported in DMAR table in the ATSR scope to let the OS know how to handle these devices the right way when VT-d is used. Add code to create an entry for a PCI root port using the type "SCOPE_PCI_SUB". Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15912 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
DMAR tables can contain so called "Address Translation Service Reporting" (ATSR) structure. It is applicable for platforms that support Device-TLBs and describe PCI root ports that have this ability. Add code to create this ATSR structure. In addition, a function to fix up the size of the ATSR structure is added as this is a new type and using the function acpi_dmar_drhd_fixup() can lead to confusion. Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15911 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03mainboard/intel/galileo: Remove use of EDK-II macros & data typesLee Leahy
Add assert.h to use coreboot's ASSERT macro. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15859 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03soc/intel/quark: Make ramstage relocatableLee Leahy
Relocate ramstage into CBMEM. TEST=Build and run on Galileo Gen2 Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15994 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-03drivers/intel/fsp2_0: Update the debug levelsLee Leahy
Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Remove fsp_print_upd_info declarationLee Leahy
Remove unused function declaration. TEST=Build and run on Galileo Gen2 Change-Id: Id971829c19c2535c975a68c44fb3697f60d0b4ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Disable display of FSP headerLee Leahy
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Handle FspNotify callsLee Leahy
Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. Display the MTRRs before the first call to fsp_notify. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: FSP driver handles all FSP errorsLee Leahy
Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInitLee Leahy
Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15850 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add display HOB supportLee Leahy
Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into util.h * Move hob_type enum into util.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add UPD display supportLee Leahy
Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15847 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Monitor FSP setting of MTRRsLee Leahy
Display the MTRR values in the following locations: * Before the call to FspMemoryInit to document coreboot settings * After the call to FspMemoryInit * Before the call to FspSiliconInit * After the call to FspSiliconInit * After the call to FspNotify * Before the call to FspNotify added in patch 15855 TEST=Build and run on Galileo Gen2 Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15849 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02libpayload: split "Drivers" config section in KconfigAntonello Dettori
Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15914 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-023rdparty/chromeec: Update submodule to latestMartin Roth
From: 388a7fa8 (Wed, 10 Feb 2016) CR50: remove incorrect output length check in RSA decrypt To: 83b6d697 (Mon, 1 Aug 2016) g: increase usb console TX buffer size to 4K 676 commits Change-Id: Ic80de8b6fd6d9eba2a092b1a3493931241a2e48b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16021 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02google/lars & intel/kunimitsu: Disable EC buildMartin Roth
The Chrome EC codebase no longer supports the google/lars and intel/kunimitsu boards. Disable the build in those platforms. Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02superio/fintek/f81866d: Add support for UART 3/4Fabian Kunkel
Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-02util/lint: Add a lint tool to find non-ascii & unprintable charsMartin Roth
This examines characters in coreboot's sourcecode to look for values that are not TAB, or in the range of space (0x20) to ~ (0x7F). It specifically excludes copyright lines so that names with high- ASCII characters are not flagged. Change-Id: I40f7e61fd403cbad19cf0746e2017c53e7379bf8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15979 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02google/reef: Add pull up 20K for LPC SERIRQKane Chen
per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a Reviewed-on: https://review.coreboot.org/15951 Tested-by: build bot (Jenkins) Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02intel/amenia: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/15777 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02soc/intel/apollolake: Add iosstate macros for GPIOShankar, Vaibhav
IO Standby State (IOSSTATE): The I/O Standby State defines which state the pad should be parked in when the I/O is in a standby state. Iosstate set to 15 means IO-Standby is ignored for this pin (same as functional mode), So that pin keeps on functioning in S3/S0iX. Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/15776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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