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2015-06-12libpayload: Rename Config.in -> KconfigStefan Reinauer
libpayload is the only Kconfig based project under the coreboot umbrella that is using Config.in as its name for Kconfig config files. Rename that to Kconfig as on the other projects for consistency. Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-12buildgcc: replace [[ ... == ... ]] with something more portablePatrick Georgi
using grep is an extra process invocation, but it's not a bashism. Also match precisely, so AGCC doesn't trigger on GCC (we don't have collisions right now, but we won't have to deal with them in the future) Change-Id: I242833c350b7f1e6a6793f288c1aae0b50d57a26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10518 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-11Clearly define printk log level use cases.Nicky Sielicki
The proper log level for any given printk statement is up to the interpretation of the developer. This results in console output with somewhat inconsistent levels of verbosity. This patch clearly defines each log level and its use case, hopefully resulting in less ambiguity for developers. The concern with this patch might be that it leaves a lot of preexisting printk statements using a log level that is inconsistent with the description. I think that *most* statements map to these extended definitions very nicely. The most discrepancies are between debug and spew, but I'm willing to say that 95% of statements with a level lower than debug are correct by these definitions. There was some discussion dating back to 2010 on the mailing list about renaming these constants to lose the 'BIOS_' prefix and to consolidate some of them into a single constant. I disagree that it is necessary to merge any of them, I think they all have unique use cases. But I do think that if you all agree with these definitions, it might be useful to rename them to reflect their use cases. I also will add that I believe removing BIOS_NEVER is a good idea. I do not see the use case, and it's used in only 4 files. Change-Id: I8aefdd9dee4cb4ad2fc78ee7133a93f8ddf0720b Signed-off-by: Nicky Sielicki <nlsielicki@wisc.edu> Reviewed-on: http://review.coreboot.org/10444 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-113rdparty/blobs: Move submodule marker forwardMarc Jones
New marker includes: 3d5af98 microcode: Update Broadwell to MC0306D4_0000001F 349fd55 microcode: Update Baytrail to M0C30678_000082D 9077293 Add BLOBs to support AMD Embedded "Merlin Falcon" processor Change-Id: I53f8f95079c6436ad316a11d432fcf92c03332b5 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10506 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-11kconfig: enforce stable sort orderPatrick Georgi
Locales differ in the order in which they sort entries. This ensures predictable behavior. Change-Id: I4ceec90a56bbc368a847d14298db0a21cc21e77c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10510 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-11lenovo: Hide SMBIOS configVladimir Serbinenko
It's derived from EEPROM on Lenovo machines and not from user config which is ignored. Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7055 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-06-10mips: implement arch_segment_loaded callbackIonela Voinescu
This change adds cache management after loading stages. Before jumping to a new stage we should flush the data caches to memory and invalidate instruction cache. After all segments are loaded CBFS cache is also flushed. With this change all stages of coreboot are now executed successfully. This was tested on Pistachio bring up board, also known as Urara. Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10456 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-10mips: CBMEM table reference is passed to payloadIonela Voinescu
The coreboot table address is passed as an argument when jumping to payload. With this change depthcharge is loaded and executed properly on urara. Change-Id: I230d474a91b8d38aff070aa4aac623b6c8f0809c Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10pistachio: sort included header filesIonela Voinescu
Place included header files in alphabetical order. Change-Id: Ice23178d1f07e2cb0178efbc7ce487d54bf3f708 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10pistachio: initialize cbmem area to be emptyIonela Voinescu
Use cbmem_initialize_empty() after DDR configuration so that cbmem is always initialized from scratch on each boot. Change-Id: Ic9ca34867b26aab82cf3154280694b6fb61ee11f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10458 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-10AMD PI: remove unuseful ACPI codeWANG Siyuan
sata.asl and superio.asl are empty files. Remove them. Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10kconfig: Reorder config includesDuncan Laurie
The default ordering for the base kconfig entries has the CPU directory coming before the SOC directory, which means that the values in the CPU Kconfig take precedence. The first visible consequence of this is that CONFIG_SMM_TSEG_SIZE will be set to 0 on all SOC implementations. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: Ifd56a2ceb73ab335a86126e48d35ff4c749990ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0cddae37d3de1cbf3dd6afcf4a0707b7af9436fa Original-Change-Id: I98e3bf249650b50667dde62b6be9c1bf587ad0b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/276189 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10478 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10rockchip: rk3288: add HDMI related iomux configurationhuang lin
BUG=none BRANCH=none TEST=Boot from mickey board Change-Id: I6eadf52bddcf89011a112a8e5dee5e752556add9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e3c865f0bf8567c3183d7948a0f9e8361db70695 Original-Change-Id: I438527ee0870044f48b23a6842986e7cf166e191 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276290 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/10477 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10ARM64 rmodule: Add new reloc type R_AARCH64_CONDBR19Furquan Shaikh
BUG=chrome-os-partner:41185 BRANCH=None TEST=Compiles successfully for ryu. Change-Id: I78ccc4b5ef8b49bae533e5a82323f07aaab01a7e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf9d288d4bbc91301dc814408bf5e3686b869974 Original-Change-Id: I24df0eb51883a634ec3d26d46f79a059a4f8394a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/275749 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10476 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-10google/auron: Add initial mainboard copy from PeppyMarc Jones
Copy the Peppy directory. No changes. Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10499 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10mainboard/lenovo/t400: Add initial ATPX ACPI implementationTimothy Pearson
Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9320 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10buildgcc: build with bfd and gold linkerStefan Reinauer
Build with bfd and gold linker, but use bfd linker per default and make sure that lto is enabled in both binutils and gcc Change-Id: I0584396b4580674cfdca24fbed0d8eeb1ee38806 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10496 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10buildgcc: move to a package centric user interfaceStefan Reinauer
Instead of building IASL and GDB implicitly when building GCC, this patch changes buildgcc to let you explicitly specify what you want to build. This will prevent IASL from building over and over again, when all you need is GDB. The new command line option is -P | --package <package> where package is one of the following: GCC, GDB, CLANG, IASL If no package is specified, buildgcc will default to GCC. Change-Id: I8836bed16fc2bc39e0951199143581cc6d71cb4d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10492 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-10google/jecht: Remove whitespace at EOLKyösti Mälkki
Change-Id: I707802befe5b8aaafafc34b17cbdfe795777b6f6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10501 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-10smbios: Fix type1 family settingMarc Jones
The type1 family setting from chromium was mis-merged into the type2 function. Move it to the correct type1 function. Bad commit: 51bdc4781635b99d89e6b7a414a2172be8cb690c Change-Id: I72e6ef80bbf185a39fcf169c8247dc16462e6bc3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10498 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-10lenovo/t400: Fix buildKyösti Mälkki
Change-Id: I8e8b6e7c123e641749c42a7c706176e285902bb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-10buildgcc: fix compilation of IASLStefan Reinauer
IASL was broken when compiling without GCC. Change-Id: Ib859ce41c1dda10181781c025fc378504f5ebb91 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10495 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10buildgcc: Update and fix GDBStefan Reinauer
GDB stopped building ever since we updated from version 7.6 but nobody noticed ;) Update from 7.9 to 7.9.1 and bring the required patches forward. Change-Id: I2f357525a46d5540e9f57b80d830943bbd5dfcaf Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10494 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10buildgcc: Reorder main programStefan Reinauer
This groups all tasks happening in the main program, orders them according to their dependencies and adds comments on the various tasks. Change-Id: Ib62bd213977cbc3307ef62e9a7e64515563968c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10490 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
2015-06-10buildgcc: Don't use BUILDDIRPREFIXStefan Reinauer
Change-Id: I7be9b39a0d92882fa437f666d7f4a85e6f0a23f6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10489 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-10buildgcc: solidify and remove boilerplate codeStefan Reinauer
- don't capture build_$package in a subshell by piping it - move HOSTCFLAGS to build_GMP - only create a build directory if a build happens - automatically collect packages to build Change-Id: Ic5a9f3f222faecd3381b413e5f25dff87262a855 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10475 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo/t400: Remove X200-specific codeTimothy Pearson
Change-Id: Ic3503938b996bbf31f1417923f019a7bc722b9fd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10429 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo: Copy X200 board to T400 for future expansionTimothy Pearson
Change-Id: If2d48b84fe7bd7b144e96171e54067891e3c4e2e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9316 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10mainboard/lenovo/x200: Add power_on_after_fail NVRAM optionTimothy Pearson
Change-Id: I8e78cbae132566b6ca27e0a68af2656364c82b8f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9332 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10resource: Refactor IORESOURCE flags useKyösti Mälkki
The type of a resource is really an enumeration but our implementation is as a bitmask. Compare all relevant bits and remove the shadowed declarations of IORESOURCE bits. Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8891 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10PCI subsystem: Drop PCI_64BIT_PREF_MEM optionKyösti Mälkki
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10northbridge/amd/amdfam10: Increase MMIO hole size to 1GBTimothy Pearson
On modern mainboards with multiple PCI-e devices and a single graphics card the default MMIO hole size of 512M is inadequate, leading to resource-hungry PCI-e devices (such as an external graphics card) being assigned invalid MMIO ranges. This, in turn, causes the entire PCI subsystem to become unavailable, leading to a failure to boot. TEST: Booted KGPE-D16 with NVIDIA 7300LE and verified proper operation of PCI/PCI-e devices, including text mode VGA operation via the add-on card and its VGA option ROM. Change-Id: I8d25f4b19f2d0860644ab1ee002c15041437121f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10428 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10northbridge/amd/amdmct: Honor MMCONF_BASE_ADDRESSTimothy Pearson
The MMIO hole start address was hardcoded on AMD Family 10h systems. Use the MMCONF_BASE_ADDRESS Kconfig setting instead. Change-Id: I204e904d96d14e99529fa5e524fd73e6ea256dc0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
Change-Id: Idd05a16bd9bd31438437ef229aa87f55da8489fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10467 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10466 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10util/kconfig/Makefile: Add savedefconfig targetMartin Roth
Add a savedefconfig target and the help for it to the kconfig makefile. The main advantage I found for using defconfigs instead of the full .config is that they require less maintenence, so long as reasonable default values are set when adding new config options. When the defconfig is expanded, it will use default values for all options not saved in the defconfig. This cuts the size of a saved config from 500ish lines to roughly 20 lines. savedefconfig was added to the linux kernel in commit id 7cf3d73b4360e91b14326632ab1aeda4cb26308d Change-Id: I45f3dc87b773fb6e9ee53e32fdcafff1f53074d2 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10462 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09buildgcc: use ${GDB_DIR} instead of gdb-${GDB_VERSION}Stefan Reinauer
Bring gdb in sync with all other build targets. Change-Id: I9c478947a00f044edf910a91d876bbf486a791cf Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10488 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-09buildgcc: Fail if a patch failed to applyStefan Reinauer
Otherwise one could end up with what they think is a coreboot toolchain but in fact it'd be missing some patches. Change-Id: Ic451f7061b822d0f4b64acc9976ba81fd544e85b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10487 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-09buildgcc: Don't run autoconfStefan Reinauer
gcc and binutils fixed their upstream tar balls, and running autoconf created more problems than it solved Change-Id: I0003dd597f521701405ff35923214435136b262d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10486 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-09buildgcc: move from if test to if [ .. ]Stefan Reinauer
Change-Id: I29fe23e377045f08b8212742d84c2ee2b4a61b15 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10485 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-09buildgcc: move from `..` to $( .. )Stefan Reinauer
Change-Id: I7a095470d408d013a4a915e010c59ea99ca1f1c8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10484 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-09vboot: add new firmware indiciesAaron Durbin
Some patches landed that didn't introduce the Kconfig options for additional firmware components. Add them. Change-Id: I0a0b7f0291389d126a7c491f710618a278cfb5d7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09x86: remove printk() from init_timer()Aaron Durbin
For console drivers which use udelay() we can deadlock in the printk path on the spinlock. The reason is that on the first call to udelay() from within a console driver it will go back down the printk() path deadlocking oneself. Just remove the printk() as it was asymmetric on romstage vs ramstage. Change-Id: I30fe7d6e5b4684f17d4f353c0816b64f9242de0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10483 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-09pistachio: increase romstage sizeIonela Voinescu
This change is necessary to support future additions to romstage. Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10457 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
Instead of having the chipset code make the approrpiate calls at the appropriate places use the cbmem init hooks to take the appropriate action. That way no chipset code needs to be changed in order to support the external stage cache. Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09cbmem: add indicator to hooks if cbmem is being recoveredAaron Durbin
It can be helpful to certain users of the cbmem init hooks to know if recovery was done or not. Therefore, add this as a parameter to the hooks. Change-Id: I049fc191059cfdb8095986d3dc4eee9e25cf5452 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09device/device.c: Improve output in `init_dev()`Paul Menzel
Since commit 05294292 (device tree: track init times) there are two lines printed for each init() call of a device, when `HAVE_MONOTONIC_TIMER` is selected. […] CPU_CLUSTER: 0 init 12708 usecs DOMAIN: 0000 init DOMAIN: 0000 init 1 usecs PCI: 00:00.0 init Northbridge init PCI: 00:00.0 init 2 usecs PCI: 00:01.0 init PCI: 00:01.0 init 1 usecs PCI: 00:01.1 init PCI: 00:01.1 init 1 usecs PCI: 00:11.0 init PCI: 00:11.0 init 1 usecs PCI: 00:14.0 init PCI: 00:14.0 init 1 usecs PCI: 00:14.3 init SB800 - Late.c - lpc_init - Start. RTC Init RTC: coreboot checksum invalid SB800 - Late.c - lpc_init - End. […] Improve the output by changing the wording to. %s init ...\n init() %s init finished in %ld usecs\n Note, that `%s init ... done in %ld usecs` is not possible as the function `init()` can also print messages. Change-Id: I7132cd650911dba680f060d6073a5a09c879b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-09genbuild_h: set LC_ALL=C to get rid of language influence to dateAlexander Couzens
Change-Id: Ia0af9e332522a640dd9aaa3a62d39d691fcfa959 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/10449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09genbuild_h: refactor environment variable into export'sAlexander Couzens
Change-Id: Ife3fb0c86fbd065fe9957bbc79b4dd1391f930b2 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/10448 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 15:42:59 +0000