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2017-06-09purism/librem13v2: Enable SATA, disable eMMC supportYouness Alaoui
Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add microcode values in KconfigYouness Alaoui
The FSP Temp RAM init will fail if the mircocode values are set to 0. A valid microcode update needs to be included and its size and offset need to be set in the config. Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19936 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add memory init codeYouness Alaoui
Adding code to setup the spd information from sodimm. Adapted from intel/kblrvp. Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09purism/librem13v2: Add GPIO pad configurationYouness Alaoui
The GPIO configuration matches the one from the original BIOS. Some configs don't make much sense, but I kept it as is so it would match (such as a NC pin with TX set to 1, or RXINV enabled). Remove unnecessary early GPIO config. Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19934 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Select SERIRQ_CONTINUOUS_MODEMatt DeVillier
Like other devices using ENE embedded controllers, the librem13v2 requires this config option for the PS2 keyboard and mouse (trackpad) to function properly. Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add initial directory for librem13 v2Youness Alaoui
Add the initial directory for the port of the Librem 13 v2. The base implementation was copied from the google/chell directory and the chell references were replaced. spd directory was removed since the RAM is not soldered on the MB. The Kconfig, board_info.txt and devicetree.cb files were modified to match the Librem 13 v2 hardware information. The romstage.c, mainboard.c, Makefile.in and dsdt.asl were modified to remove chromeos specific code. The boardid.c, chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c files were removed from the tree, and the acpi directory was replaced with the acpi directory from the purism/librem13 board. These changes allow us to remove the references to chromeos specific code and allow coreboot to compile when the librem13v2 board is selected. Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v1: Set FADT revision to ACPI 3.0Matt DeVillier
The FADT revision was set to 5, but we do not implement the ACPI v5.0 specification, which prevents Windows from booting. Setting it to v3 (matching most other boards) fixes the issue and Windows now boots normally. Bug found by Matt DeVillier, fix tested by Youness Alaoui on Librem 13 v1 hardware. Please also see commits 00d250e2289de (intel/skylake: Switch FADT to ACPI version 3.0) [1] and 27e6042bb7d0b1 (intel/apollolake: Switch FADT to ACPI version 3.0) [2]. [1] https://review.coreboot.org/19453 [2] https://review.coreboot.org/19146 Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09pciexp_device: Remove useless write on a read-only registerYouness Alaoui
The Role-Based Error Reporting is not a configurable field, it's a read only field in the Device Capability register. This code was old and comes from commit f6eb88ad but evidently is not useful in any way. The PCIe Specification [1] states that it's read-only and must always be set to 1. I have also done tests on purism/librem13 hardware, trying to change that value, without any success. [1]: PCI Express Base Specification Revision 3.0 Page 612 Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09soc/broadwell: Allow disabling of PCIe ASPM optionsYouness Alaoui
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM) are hardcoded for broadwell chips, but some boards may not support these ASPM options even if the SoC does support it (non-wired CLKREQ pin for example). This is required to disable L1 substates on the Purism/Librem 13 which seems to have issues with NVMe drives falling into L1.2 state and not being able to exit that state. Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09pciexp_device: Prevent race condition with retrain linkYouness Alaoui
The PCIe specification[1] describes a race condition that can occur when using the Retrain Link bit in the Link Control Register. The race condition is avoided by checking the retrain link bit in the link status register and waiting until it is set to 0, before initiating a new link retraining. [1] PCI Express Base Specification Revision 3.0 Page 633 Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v1: Rename librem13 to librem13v1Youness Alaoui
A simple rename of the directory and the config values and string in Kconfig/Kconfig.name/board_info.txt It will be less confusing for users since the first models are referred to as 'v1' everywhere now. Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19931 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-09soc/baytrail: fix ACPI table by recollecting TOLMMatt DeVillier
Adapted from Chromium commit 8fbe1e7 for soc/braswell (also review.coreboot.org/#/c/20060/); same issue affects baytrail as well. This patch recollects TOLM accessing; as Aaron recalled some core_msr_script turns off access to TOLM register, he suggests to store tolm to avoid getting back a zero while setting acpi nvs space. Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/baytrail: assign unique DMA request lines to I2C controllersMatt DeVillier
Each I2C controller should have a unique pair of DMA request lines, and DMA channels should be assigned incrementally, rolling over as necessary. Source: Intel Baytrail/ValleyView UEFI reference code Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/braswell: assign unique DMA request lines to I2C controllersMatt DeVillier
Each I2C controller should have a unique pair of DMA request lines, and DMA channels should be assigned incrementally, rolling over as necessary. Source: Intel Braswell UEFI reference code Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09nb/intel/fsp_sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
Use common init_igd_opregion method. Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09nb/intel/common: Create a common init_igd_opregion methodPatrick Rudolph
Copy Haswell's init_igd_opregion to common folder. Remove platform specific code. Will replace all Intel NB implementations. Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09device/dram/ddr2.c: Fix is_registered_ddr2Arthur Heymans
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD specifications. Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-09msrtool: Remove `no-pic` from `CFLAGS`Paul Menzel
Commit 7c634ae8 (msrtool: added support for Intel CPUs) adds `no-pic` to the compiler flags. GCC 7.0.1 20170316 fails to built with the error below. ``` /usr/bin/ld: msrtool.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: msrutils.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: sys.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: linux.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: freebsd.o: relocation R_X86_64_32S against `.data' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: final link failed: Nonrepresentable section on output ``` Removing the flag causes the build to succeed with GCC 7, 6.3, and clang 4.0. Change-Id: I3d7aed27ce7f84aa27305c68e2d5f14607c58ec8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09soc/braswell: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for intel/strago and google/cyan as to not break compilation. Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09google/chell: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09soc/skylake: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09cpu/intel/model_206ax: Use tsc monotonic timerPatrick Rudolph
Switch from lapic to tsc. Allows timestamps to be used in coreboot, as there's a reference clock available to calculate correct time units. Clean Kconfig, remove duplicated lapic code and include tsc dir for LGA1155 boards. Tested on Lenovo T430. Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09inteltool: Add Skylake PCI id in memory.cNico Huber
Change-Id: I751e887bd90a258a69d13ea4ee9a409c8c86a3c3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09mb/google/soraka: Update UF camera i2c addressNaresh G Solanki
Update user facing camera i2c address to 0x36. BUG=None TEST=Build & boot on soraka. Make sure user facing camera is detected. Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-06-09rx6110sa: Add more chip configuration options to chipWerner Zeh
The RTC RX6110SA has several configuration options which might be interesting to set. To make this setup independent of the driver itself but let it still be configurable on mainboard level, add more configuration options to the chip driver. Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-06-08crossgcc: Resolve pointer and integer comparison in GCCPaul Kocialkowki
GCC version 7 is being a bit picky about pointer and integer comparison by default, which triggers a crossgcc build error. This backports a patch from upstream GCC to fix the issue. Change-Id: I8b1e806c10604c0df080ac5edc667bf1141e2c17 Signed-off-by: Paul Kocialkowki <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/20103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
Provide all gfx init methods as a Kconfig `choice`. This elimates the option to select native gfx init along with running a Video BIOS. It's been only theoretically useful in one corner case: Hybrid graphics where only one controller is supported by native gfx init. Though I suppose in that case it's fair to assume that one would use SeaBIOS to run the VBIOS. For the case that we want the payload to initialize graphics or no pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the choice. If multiple options are available, the default is chosen as follows: * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS, * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS, * NATIVE_VGA_INIT, if we don't add a Video BIOS. As a side effect, libgfxinit is now an independent choice. Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-083rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit to the latest master. Changes: * Remove trailing whitespace in debug output. * Change some types to make it verify with SPARK Pro. * Add Broxton (Apollo Lake) support for eDP/DP/HDMI. * Add Linux user-space test tool `gfx_test`. * Add a README describing libgfxinit and the build process. TEST=Booted lenovo/t420 and verified that internal and external displays are working. Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-083rdparty/libhwbase: Update submodule pointerNico Huber
Update libhwbase to the current master. Some noteworthy changes: * Add prerequisites for upcoming Apollo Lake support in libgfxinit. * Add some support for Linux user-space for libgfxinit's `gfx_test`. * Fix compilation with GCC 7. Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-08nb/intel/sandybridge/raminit: Advertise correct frequencyPatrick Rudolph
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the reference clock can be 100Mhz. Decode the register and use the reference clock to calculate the selected DDR frequency. Tested on Lenovo T430. Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-08arch/x86/acpigen: Add additional opcodesPatrick Rudolph
Add additional ACPI opcodes, that are going to be used in the following commits. Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-08drvs/intel/wifi/wifi: Fix regressionPatrick Rudolph
Fix regression introduced by commit 5c026445 (drivers/intel/wifi: Add support for generating SSDT table) In case the regular PCI path is taken, there're no chip_ops and the code will segfault. The bug was covered by other bugs that caused this code to never execute. Add NULL pointer checks and only fill in device name if one is provided. Tested on Lenovo T430 and wifi card 8086:0085. Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-06-07util/lint: Give better warning for help spacing issueMartin Roth
Because the help block uses significant whitespace to determine whether or not text is inside the help block, a mixture of spaces and tabs confuses the parser. If there's an unrecognized line, and the previous line was inside a help block, it's likely that this line is too. Additionally, this was found with a line that started ' configuration', and threw a perl warning about an uninitialized value because the parser thought this was the start of a new config line, but couldn't find the symbol. Now we make sure that config statements have whitespace after the 'config' statement. Change-Id: I46375738a18903b266ea9fff3102a1a91235e609 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-07Makefile: add 'filelist' targetMartin Roth
Add a target to show what files are used in the build. This was already being generated for other targets, but there was no target to just generate and view the list. Change-Id: I6998296bb135d8b7170cacae2be902ef9dac7b54 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07util/lint/kconfig_lint: update help checkingMartin Roth
- Turn the check for help text with no indentation from a warning to an error. - Show an error if the help text is at the same indentation level as the 'help' keyword. Change-Id: Ibf868c83e2a128ceb6c4d3da7f2cf7dc237054e6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-06-07spi: Remove unused/unnecessary spi_init function definitionsFurquan Shaikh
Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-07mainboard/google/poppy: Add support for ELAN deviceFurquan Shaikh
Add support for ELAN 5515 device. BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-07Kconfig: Indent help textMartin Roth
These Kconfig files had help text that was not indented further than the 'help' keyword. Change-Id: Ia9fdb22c0f5f0cec0c9d08aa6603b4ce8d60d9a3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-07abuild: Remove space before tabPaul Menzel
Fix up commit 26174c97 (abuild: Build saved config files) unintentionally adding a space before a tabulator. Change-Id: Ic51dee6ed9d640335c2bde5bd5dfad3691c505e0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-07intel/common/acpi: Fix ACPI debug log issue with LPSS UARTSubrata Banik
This patch fixes ACPI debug print issue reported internally while using APRT asl method. Potentially some junk characters gets added into final print buffer due to LPSS MMIO register space is 32 bit width and ADBG is one byte at a time. TEST=Built and boo eve to ensure to be able to get ASL console log without any corruption. Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07payloads/Kconfig: Add NO_DEFAULT_PAYLOADNico Huber
This symbol can be selected (e.g. in site-local/) to disable the user friendly but annoying default payload choice. Change-Id: I2f72d4efc0a428dce377c3d003b2c00a6c8d4c08 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19808 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07payloads: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-07Use www.coreboot.org over coreboot.orgPaul Menzel
<https://coreboot.org> is redirected to <https://www.coreboot.org>. ``` $ curl -I https://coreboot.org HTTP/1.1 301 Moved Permanently Server: nginx/1.8.1 Date: Mon, 05 Jun 2017 10:41:33 GMT Content-Type: text/html Content-Length: 184 Connection: keep-alive Location: https://www.coreboot.org/ ``` So use the command below to use the final location to save a redirect. ``` $ git grep -l https://coreboot.org \ | xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g' ``` Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20035 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07via/epia-m700: Wrap long line in commentPaul Menzel
Wrapping the long line tries to address a warning by `checkpatch.pl`, but the line is still over 80 characters long. Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20033 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-06asus/kgpe-d16: Add video card ID for VGA BIOS namePaul Menzel
The comma-separated PCI vendor and device ID is used to associate the VGA BIOS to the video device by using it as the file name of the VGA Option ROM. Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06nvramcui: Use regular `if` over `#if` for `IS_ENABLED`Paul Menzel
When using the regular `if` construct, the compiler will check the guarded code independently from the condition. Change-Id: I988fa9379e8c748013a67ef29fa908b4d9a970ad Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 17:42:33 +0000