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2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21cyan: Enable EC software syncRavi Sarawadi
BUG=chrome-os-partner:40526 BRANCH=None TEST=Verify that system boots when used with coreboot and EC versions that also have Software Sync enabled. Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00 Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0 Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283573 Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/10985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Revert "northbridge/amd/pi: Add support for memory settings"Marc Jones
This is breaking the build right now. Reapply once the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f Reviewed-on: http://review.coreboot.org/11020 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21amd/hudson: Fix makefile FWM location checkMarc Jones
Fix typo. Use the correct math helper int-lt. Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21braswell: clean up \_PR entriesJagadish Krishnamoorthy
All \_PR entries needs to be changed from CPU# to CP## so that it can support more cores. BRANCH=none BUG=chrome-os-partner:38734 TEST=build and boot cyan/strago boards. Change-Id: I80a79ec8edbce46826140470645b7532ae361f91 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1 Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285700 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-20northbridge/amd/pi: Add support for memory settingsDave Frodin
This adds support for binarypi based boards that have to make adjustments to the memory configuration settings. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10672 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-18cbfstool: Deduplicate code to merge empty filesPatrick Georgi
The code for removing a file had its own merge routine. Use the generic one instead. Change-Id: I90ed007ab86f78a2728f529fa0143c5c1dfbbdc3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18cbfstool: rename checksum to attributes_offsetPatrick Georgi
So far it's still unused, but its purpose will change: It will become an offset to another structure that contains additional file attributes. This change is compatible because the binary format doesn't change and so far the field was always set to 0, which can serve nicely as 'unused' field. Change-Id: I2dafb06866713d43a236556f9492641526270837 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18Makefile: Fix KCONFIG_AUTOHEADER dependenciesStefan Reinauer
This makes the Makefile more robust when changing the file name or changing the .config outside of make *config Change-Id: Ifc013cc3ef899a7846742a961261ac50bc67e27b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-18libpayload: usb: Add support for SuperSpeed hubsJulius Werner
This patch adds support for the SuperSpeed half of USB 3.0 hubs, which previously prevented SuperSpeed devices behind those hubs from working. BRANCH=None BUG=chrome-os-partner:39877 TEST=Played around with multiple hubs and devices on Oak and Falco, can no longer find a combination that doesn't work. Change-Id: I20815be95769e33d399b7ad91c3020687234e059 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284577 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com> Reviewed-on: http://review.coreboot.org/10958 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18libpayload: usb: xhci: Prevent address reuseJulius Werner
We have been trying to avoid reassigning previously used USB addresses to different devices since CL:197420, because some devices seem to take issue with that. Unfortunately, that patch doesn't affect XHCI: those controllers insist on chosing addresses on their own. The only way to prevent them from reusing a previously assigned address is to not disable that slot at all. This patch implements address reuse avoidance on XHCI by not disabling slots when a device is detatched (which may occur both on physical detachment or if we simply couldn't find a driver for that device). Instead, we just release as many resources as we can for detached devices (by dropping all endpoint contexts) and defer the final cleanup until the point where the controller actually runs out of resources (a point that we probably don't often reach in most firmware scenarios). BRANCH=none BUG=chrome-os-partner:42181 TEST=Booted an Oak plugged into a Servo without having a driver for the SMSC network chip, observed that it could still enumerate the next device afterwards. Kept unplugging/replugging stuff until the cleanup triggered and made sure the controller still worked after that. Also played around a bit on a Falco without issues. Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284175 Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10957 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18amd/pi: Increase assumption for maximum CBFS file header sizePatrick Georgi
The new attributes increase the header size, breaking this assumption. Change-Id: Ib23862f27650b39133deafb74a24327b098b6e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10942 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-18cbfstool: move fill value to cbfs.hPatrick Georgi
Change-Id: Ie05db6d43219c65d08e2221009875f81eb29b630 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18intel/kunimitsu: Fix Kconfig symbol typePatrick Georgi
BOOT_MEDIA_SPI_BUS is int, not hex. Change-Id: I5cbcc3889a025caab921208037c8a61d224078a7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10973 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-17soc/intel: Remove microcode terminatorsStefan Reinauer
They have been removed in the rest of the code already. http://review.coreboot.org/#/c/4506/ Change-Id: I232cc2ccd4dd90359de4ab710486db65667500f4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-17intel/sklrvp: remove trailing whitespacePatrick Georgi
Change-Id: If933a70992a6ae8228eef8d4f0386387b4e4549d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-17skylake: remove whitespace from ASL filesStefan Reinauer
Found by the commit hooks. Change-Id: I9baa90ca0111ddc9cb69cbb7dd17f63e8a98a04f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10965 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-17mainboard/google: Add Braswell based Cyan boardLee Leahy
Add initial files for the cyan board. Matches chromium tree at 927026db This board uses the Braswell FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10182 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Skylake based Kunimitsu boardLee Leahy
Initial files to support the Kunimitsu board. Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run ChromeOS on kunimitsu Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Skylake based RVP3 boardLee Leahy
Initial files to support the Intel Skylake RVP3 Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Braswell based Strago boardLee Leahy
Add the initial files to support the Intel RVP for Braswell. Matches chromium tree at 927026db This board uses the Braswell FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run ChromeOS on strago Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17lint/gitconfig: Enable checkpatch.pl checking of commitsStefan Reinauer
This patch enables running the checkpatch script on the code portion of each commit as part of the pre-commit hook. At this point there is no checking of the commit message in place (e.g. for typos) Change-Id: I7cdf0692cf372986e411f4aba4691417b73c7511 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8419 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-17indent style fix for lapic_cpu_init.cJonathan A. Kollasch
Change-Id: I2821aaed1bc6324e671f68e4e4effb9dd006dcd9 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10922 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-17Remove unused Kconfig symbols in c codeMartin Roth
The BROKEN_CAR_MIGRATE symbol was removed in commit a6371940 - x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option The symbol DISABLE_SANDYBRIDGE_HYPERTHREADING is from Sage, and was never added to the coreboot.org codebase. Change-Id: I953fe7c46106634a5a3fcdaff88b39e884f152e6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10941 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16libpayload: usb: dwc2: support split transactionYunzhi Li
With split transaction, dwc2 host controller can handle full- and low-speed devices on hub in high-speed mode. This commit adds support for split control and interrupt transfers BUG=None TEST=Connect usb keyboard through hub, usb keyboard can work BRANCH=None Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019 Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283282 Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: new sdram_lp0_save_params() functionYen Lin
New sdram_lp0_save_params() function for T210. Due to its size, move the function from romstage to ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug; and check scratch registers Change-Id: I420ac4c15262f2c6307bcd84beb6c5da0310c7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38860895938c40062a9f860f75e31a539f15992b Original-Change-Id: Iaa478969458946faedd295578fe7d72b5a32e701 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277022 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0 BUG=chrome-os-partner:40741 BRANCH=None TEST=build Foster ok; and check scratch20 register Change-Id: I2c203317e6305214b74430780f2fe7b15652873a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0a99ac9c7db267129e4bc3478f9bb1ece08507 Original-Change-Id: I7be10d5deb5118f1cf3e339afca94893610437f2 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280291 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10955 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0. BUG=chrome-os-partner:40741 BRANCH=None TEST=build Smaug ok; and check scratch20 register Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343 Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277024 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10954 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: correct odmdata location in bctYen Lin
Correct the odmdata location in bct for T210. BUG=chrome-os-partner:40741 BRANCH=None TEST=build ok on Smaug Change-Id: I2258556ec5cf5d25782e60e084f3d5657b441c86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 288a5d71c35fbea1812ad0c91f2c6c5f5a022363 Original-Change-Id: I0efb033442c2aafc7f44898c16b3e91946e092d5 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277023 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: add sdram_configs.cYen Lin
Add sdram_configs.c to both romstage and ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Foster Signed-off-by: Yen Lin <yelin@nvidi.com> Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1 Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb Original-Reviewed-on: https://chromium-review.googlesource.com/280290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/10951 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: ramstage: include sdram_configs.cYen Lin
get_sdram_config() (in sdram_configs.c) will be needed in ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277373 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10950 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Use VNBN_FLASH instead of VBNV_ECFurquan Shaikh
CQ-DEPEND=CL:285312 BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ib90333e3331a90b4539d49e1a72833fe3385879f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 042fc1a451081780f8af35af6943130f6412ca5f Original-Change-Id: I729996c04d8bd6a627421803a59037d7c47a3e98 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285345 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Reorganize memlayout.ldFurquan Shaikh
Take up space from PRERAM_CBMEM_CACHE and increase verstage and romstage sizes. BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I7fdd6c08f3ca1998a6220edd80a570816ec65ab5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cce3d7baa7446e227d3da41341d9e273d4195299 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285344 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Change-Id: I6d97a60b26fbbb29a875285c46724fb43b5fe5ab Original-Reviewed-on: https://chromium-review.googlesource.com/285533 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/10948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: SPI driver cleanupFurquan Shaikh
1. Get rid of spi_delay - Instead have a tight loop to check for the spi status 2. The first check for SPI operation complete i.e. FIFOs have been processed is the SPI_STATUS_RDY bit. Thus, tegra_spi_wait should check for this bit before reading BLOCK_COUNT or any other fifo count field. 3. Flush both TX and RX FIFOs for SEND and RECV operations for PIO and DMA. 4. No need to check for rx_fifo_count == spi_byte_count to determine pio_finish operation. RDY bit should be sufficient to ensure that the SPI operation is complete. Added assert to ensure we never hit the case of RDY bit being set, yet rx_fifo_count != spi_byte_count for PIO. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs successfully for 10K+ iterations. Change-Id: I1adb9672c1503b562309a8bc6c22fe7d2271768e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de1515605e17e0c6b81874f9f3c49fd0c1b92756 Original-Change-Id: I5853d0df1bfd6020a17e478040bc4c1834563fe4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285141 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10947 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Correct dma_busy functionFurquan Shaikh
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA operation is complete. However, in case of ONCE mode, use STA_BSY bit to determine if DMA operation on the channel is complete. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs fine for 10K+ iterations Change-Id: If98f195481b18c402bd9cac353080c317e0e1168 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 927026db6fd910dac32dc218f28efcbc7b788b4e Original-Change-Id: Ib66bedfb413f948728a4f9cffce9d9c3feb0bfda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285140 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10946 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Increase drive strength for QSPI PinmuxFurquan Shaikh
Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per recommendations from nVidia hardware engineers. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8 Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284959 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10945 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Add PINMUX macros for drive strengthFurquan Shaikh
BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic606838639d33242b227fece9cbb019d8f3b3729 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 805831489ad80e4ed335ece458f81238af704876 Original-Change-Id: I54a730c3b97c3603a5b1981089913c58af2a42db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284958 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10944 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16toolchain: Add -mgeneral-regs-only to CFLAGS for arm64Furquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: I7eb75b215798a63157bae04d9d44dbd6f95a5715 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6e5ecf9b45fa35e3c87bf6ef4bd2ea01680c8826 Original-Change-Id: I36a20d65d7ccaa21fdeb6070d43c2bb0ae22a16b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285553 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10959 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16release: add release scriptPatrick Georgi
Change-Id: Ib3cd29cf1875e7ad182262d7caa33ff35f28aa85 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16cbfstool: Remove extra comma after {0, NULL} list elementSol Boucher
Trailing commas are useful for lists that can be extended. These lists are 0-terminated, and there should be no elements following that. Change-Id: Iea8c6d5579d6363e77e1f5af666948160c4a9bf9 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10932 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: Factor out compression algorithm listSol Boucher
Parse compression algorithm arguments using a single list. Change-Id: Idc5b14a53377b29964f24221e42db6e09a497d48 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: rename fieldSol Boucher
With introducing hash algorithms, 'algo' is ambiguous, so rename it to 'compression' instead. Change-Id: Ief3d39067df650d03030b5ca9e8677861ce682ed Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10930 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: move bit swapping macros to swab.hSol Boucher
Change-Id: Id22232c45225011951e01c370e0f473af574d758 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: use variable length array to model cbfs_file's filenamePatrick Georgi
Change-Id: Ib056983630b2899d7e6cbcb43f6b7153f0f8e282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10928 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: improve specification of struct cbfs_filePatrick Georgi
Lock down its size and document some of the fields Change-Id: I09fd6c80185345da0ae17d0f4498b50995fd1ec5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-16x86 realmode: Set up the 8254 timer before running option romzbao
If the 8254 is not set up, the external graphics option rom hangs and never returns. The code is tested on AMD/bettong. Change-Id: I0022de9d9a275a7d4b7a331ae7fcf793b9f4c5f5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10903 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-16AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST checkzbao
This is a result of the Silcon Observation. On warm reset, the BIST is 0x80000000, which causes BIST error. We skip checking this bit. The update will be in CZ BKDG 1.05. The code is tested on AMD/bettong. Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10902 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-07 03:52:18 +0000