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2017-03-09soc/intel/common/block: Add HECI driverAndrey Petrov
Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Prepare to use common HECI driverAndrey Petrov
Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09uti/lint/checkpatch: Fix __attribute__ struct errors for OPEN_BRACEMartin Roth
The __attribute__((weak)) lines on structs were being read as functions, causing a warning that the brace should be on the next line. Add a check to see if it's a struct with an attribute, and ignore it for the OPEN_BRACE check if it is. Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18570 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-09checkpatch.conf: Update rulesMartin Roth
- Remove the "MISSING_SPACE" check which checks for breaks at a space in a string concatenation. Most of the time this makes sense, but we occasionally need to break where there isn't a space, so having a hard rule doesn't always work. - Don't check the vendorcode directory for compliance to coreboot's code format rules. Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18569 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09uti/lint/checkpatch: add --exclude to ignore specific directoriesMartin Roth
checkpatch: add option for excluding directories when importing code from external sources Using --exclude <dir> we should be able to exclude a list of well defined locations in the tree that carry sources from other projects with other styles. This comes from the 01org/zephyr project in github: Original-Change-Id: I7d321e85eed6bc37d5c6879ae88e21d20028a433 Original-Signed-off-by: Anas Nashif <anas.nashif@intel.com> Change-Id: Icc9e841e7d84026d6ab857ff90b0f093515ccaad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18568 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09src/lib: Remove spaces after ( and before )Lee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' TEST=Build and run on Galileo Gen2 Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18636 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08mainboard/google/poppy: Add EC_HOST_EVENT_MODE_CHANGE to wakeup sourceFurquan Shaikh
Allow EC mode change event to wake AP up in S3. BUG=b:35775085 BRANCH=None TEST=Compiles successfully for poppy. Change-Id: I6f1546c60aef6620e22cdce2fab3a2709e6556a1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18608 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08chromeos/elog: Filter developer mode entry on S3 resumeDuncan Laurie
The event log entry indicating developer mode is useful for the boot path, but is not really useful on the resume path and removing it makes the event log easier to read when developer mode is enabled. To make this work I have to use #ifdef around the ACPI code since this is shared with ARM which does not have acpi.h. BUG=b:36042662 BRANCH=none TEST=perform suspend/resume on Eve and check that the event log does not have an entry for Chrome OS Developer Mode. Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18665 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-08intel/skylake: Filter suspend well power failure event for Deep SxDuncan Laurie
If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08intel/skylake: Add function to read state of Deep S5Duncan Laurie
Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Add devicetree settings for acoustic noise mitigationDuncan Laurie
Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-08google/eve: Configure GPIOs for new boardDuncan Laurie
A new board revision is making use of two previously unused GPIOs to drive BOOT/RESET pins to an on-board MCU. The reset pin is open drain so it is set as input by default, and the boot pin is driven low by default. Since these are UART0 pins they also need to be set up again after executing FSP-S as it will change them back to native mode pins. BUG=b:36025702 BRANCH=none TEST=manual testing on reworked board, toggling GPIOs to put the MCU into programming mode. Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-08libpayload-x86: Enable SSE and FPU when presentPatrick Rudolph
Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08nb/intel/nehalem/raminit.c: Refine broken commentStefan Tauner
Change-Id: Ic5c92d9a2d8bb040a04602e5da2cd37a2ae8db95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/18052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08mainboard/google/snappy: Override USB2 phy settingWisley Chen
Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08util/intelmetool: Add support for Wildcat Point LPHuan Truong
This adds support for the Wildcat Point LP for intelmetool. When the tool detected a Wildcat Point LP, then the ME will be reported as difficult-to-remove. Change-Id: I35423db11cdc1e21e7f02ce90dace7fb4d236c45 Signed-off-by: Huan Truong <htruong@tnhh.net> Reviewed-on: https://review.coreboot.org/18575 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-03-08util/intelmetool: Fix segfault on edge casesHuan Truong
The intel ME checker tool would segfault if it reaches the end of the loop without having the dev pointer set. This happens when it gets to the end of the previous loop without knowing what to do with any of the devices it sees. This patch makes sure the pointer is not NULL before accessing it. Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a Signed-off-by: Huan Truong <htruong@tnhh.net> Reviewed-on: https://review.coreboot.org/18573 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08MAINTAINERS: Update listMartin Roth
- Fix whitespace: Change some spaces to tabs - Add myself as an abuild maintainer - Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section - Add new sections for utilities: docker, toolchain, and git - Remove GENERIC DRAM section - Remove the mailing list. We don't want it to be added as a reviewer. Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08binaryPI boards: Drop any ACPI S3 supportKyösti Mälkki
None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AGESA fam10: Add missing includeKyösti Mälkki
The file is used for fam15. Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AGESA: Move heap allocator declarationsKyösti Mälkki
Definitions are not part of ACPI S3 feature, nor do they require any AGESA headers so move them to a better location. Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AMD geode: Avoid conflicting main() declarationKyösti Mälkki
Declaration of main in cpu/amd/car.h conflicts with the definition of main required for x86/postcar.c in main_decl.h. Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18615 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08mainboard/asus: Move F2A85-M_LE variant to F2A85-M.Kyösti Mälkki
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration defined, use one for both. Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson/acpi: Only declare S3 if it is supportedMarc Jones
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add early SPI setupMarshall Dawson
Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18442 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add SPI definitions to headerMarshall Dawson
Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18441 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Consolidate BITn definitionsMarshall Dawson
Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07mainboard/intel/galileo: Remove space before opening bracketLee Leahy
Fix the error detected by checkpatch and update the copyright date. TEST=Build and run on Galileo Gen2 Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix errors detected by checkpatchLee Leahy
Fix the errors detected by checkpatch and update the copyright dates. TEST=Build and run on Galileo Gen2 Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18591 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/gru: add MAX_SDRAM_FREQ config to choose max ddr freqShunqian Zheng
Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram frequency, while bob uses 800 MHz. It's normal some variants can't meet 928 MHz SI requirement and hence have to use a lower freq as spec. BUG=chrome-os-partner:61001 BRANCH=gru TEST=check dpll is 800 MHz on bob Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2 Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/420208 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com> Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55) Original-Reviewed-on: https://chromium-review.googlesource.com/448277 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18581 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/veyron: add K4B4G1646E-BYK0 ddr with ramid 000ZShunqian Zheng
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0. For clarity, sdram-ddr3-samsung-2GB now is used by - K4B4G1646D-BYK0 - K4B4G1646E-BYK0 - K4B4G1646Q-HYK0 BUG=chrome-os-partner:62131 BRANCH=veyron TEST=emerge Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4 Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/446197 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405) Original-Reviewed-on: https://chromium-review.googlesource.com/446300 Reviewed-on: https://review.coreboot.org/18519 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/veyron_*: Add new Micron and Hynix modulesDavid Hendricks
This adds SDRAM entries for the following modules: - Micron: DDMT52L256M64D2PP-107 - Hynix: H9CCNNNBKTALBR-NUD They are compatible with Samsung K4E8E324EB-EGCF, so this just copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used in the comment near the top. Notes on our "special snowflake" boards: - veyron_danger's RAM ID is hard-coded to zero, so I skipped changes involving the binary first numbering scheme. - Rialto's SDRAM mapping is different, so I padded its SDRAM entries to 24 to match other boards. - veyron_mickey requires different MR3 and ODT settings than other boards due to its unique PCB (chrome-os-partner:43626). BUG=chrome-os-partner:59997 BRANCH=none TEST=Booted new modules on Mickey (see BUG) Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3 Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com> Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com> Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6) Original-Reviewed-on: https://chromium-review.googlesource.com/446299 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18518 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix I2C driverLee Leahy
Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18029 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/poppy: fix finger print sensor interrupt gpio configurationRizwan Qureshi
Configure the right GPIOs for finger print sensor interrupt and reset lines. As per the schematics GPP_C8 is for sensor interrupt and GPP_C9 is for sensor reset. Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18389 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07nb/amd/amdht: Use variable for function namePaul Menzel
One very long line has to be wrapped to be shorter than 80 characters to satisfy the lint scripts. Note, that this gets rid of the brackets (). Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-07util/scripts/get_maintainer.pl: Remove linux tree checkMartin Roth
This was removed from the previous version, but we'd like it in a separate patch, so it's obvious and can easily be applied to the next version. Change-Id: I9396009e82e762aa0cc037dbe9e7133962af6354 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18577 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07util/scripts: Update get_maintainer.pl to latest from linux kernelMartin Roth
This is version 03aed21 from linux/scripts, updated on Dec 12, 2016. The version needs to be updated because Perl version 5.20 deprecated the /C regex expression. Perl version 5.24 removed it completely, so the old version fails to run on the coreboot builders. Change-Id: Ib97997237ca64c65d7f91d568ae4bec000804331 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18571 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07mainboard/asus: Add F2A85-M PRO variant to F2A85-M.Denis 'GNUtoo' Carikli
Status: - The primary PCIe 16x slot works: It was tested with a GPU compatible with nouveau - USB and audio are not very reliable - The ethernet card is not seen with lspci - The secondary pcie16x slot isn't working: When plugging a GPU inside, it's not seen with lspci - SATA works: The board fully boots GNU/Linux - Serial doesn't work - Populating the RAM slots might have to follow the recommended memory configuration that is described in the mainboard manual in order to be able to boot. Note that when running the shutdown command, the default boot firmware will rewrite part of the boot flash before powering off the machine. Flashing coreboot internally from the default boot fimrware can still work, if the power plug is removed after running flashrom. Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/16931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove redundant and invalid IRQ routingKyösti Mälkki
The size of the array did not match that of the actual allocation. Furthermore, the tables are written as part of set_pci_irqs() in hudson/pci.c. Also the removed code was never reached runtime, as it is only executed on ACPI S3 resume path that is currently disabled. Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18587 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove leftover s3resume includeKyösti Mälkki
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07AGESA fam14: Sanitize headerfileKyösti Mälkki
This file is only static defines. Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-03-07AGESA: Remove leftover agesawrapper includeKyösti Mälkki
Change-Id: Ib37989ee7535e59b1903537995f8383d8b04387c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07console: Enable printk for ENV_LIBAGESAKyösti Mälkki
Messages from AGESA proper are additionally controlled by various IDS parameters in board/OptionsIds.h file. Change-Id: I83e975d37ad2bdecb09c483ecae71c0ed6877731 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18545 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07Stage rules.h: Add ENV_LIBAGESAKyösti Mälkki
Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07elog: Fix duplicate event typeDuncan Laurie
The current elog implementation has two event types defined for 0xa7, apparently the result of divergent coreboot trees on chromium where some events were added to ARM systems but not upstreamed until later. Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7. BUG=b:35977516 TEST=check for proper "CPU Thermal Trip" event when investigating a device that is unexpectedly powering down. Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Clean up CPU codeSubrata Banik
Use header (soc/intel/common/block/include/intelblocks/msr.h) for MSR macros Change-Id: I401b92cda54b6140f2fe23a6447dad89879a5ef0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Use intel/common/xhci driverSubrata Banik
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-04 07:43:29 +0000