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2019-02-22intelvbttool: Add support for reading vbt from sysfsAlex Feinman
VBT on Intel(R) systems is available via sysfs as /sys/kernel/debug/dri/0/i915_vbt However the size of this file reads as 0 causing intelvbttool to fail. This patch implements incremental reads with realloc for such cases or whenever the file size is not available (e.g. reading from stdin). After this patch is applied, intelvbttool can be used as follows: sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d Change-Id: I5d17095a5747550b7115a54a7619b7294a846196 Signed-off-by: Alex Feinman <alexfeinman@hotmail.com> Reviewed-on: https://review.coreboot.org/c/31531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22mb/ocp/monolake: Fix booting issuesLukasz Siudut
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly. Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab Reviewed-on: https://review.coreboot.org/c/31435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from ↵Jeremy Soller
devicetree Tested on system76 galp3-c Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d Reviewed-on: https://review.coreboot.org/c/31535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
Add a function in gpio ASL library to set pad mode. BUG=b:123350329 Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22Update vboot submodule to upstream masterJoel Kitching
Updating from commit id a32c930e: 2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO) to commit id 1e177741: 2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE) This brings in 11 new commits. Change-Id: I59d83de49006a6d081b206716002697d39099aa4 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/31542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-22rockchip/rk3399: Fix BL31 bootmem regionsJulius Werner
The BL31 on RK3399 is split into multiple segments... the majority goes into DRAM, but small parts must be put into SRAM and PMUSRAM. With CB:31123 only the DRAM part was added to memlayout, so the SRAM parts will not be correctly marked in bootmem and BL31 loading fails the selfload check. This patch adds the remaining regions to fix the problem. Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ting Shen <phoenixshen@google.com>
2019-02-22soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD nameSubrata Banik
Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22Revert "src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260"Duncan Laurie
This reverts commit 3afb84a24583f5dee9fb407f11b32253d59392bf. Reason for revert: This is causing issues with the PCIe link and the system is unable to enter S0ix. Until it can be fixed in coreboot revert the change here that is not working properly. BUG=b:124264120 Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31559 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22mb/google/hatch: Make EC software sync enabled by defaultScott Collyer
EC software sync had been disabled because BIOS was not bundling a useful EC image. This is no longer required. This CL removes that change so EC software sync is enabled by default. BUG=b:124208414 BRANCH=None TEST=Tested with a system that have a different RW image and verified that this image was overwritten to the one bundled in the BIOS and that the EC was running its RW image. Signed-off-by: Scott Collyer <scollyer@chromium.org> Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5 Reviewed-on: https://review.coreboot.org/c/31537 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21cpu/intel/common: Add newline to set_feature_ctrl_lock() outputMatt DeVillier
Without newline, if IA32_FEATURE_CONTROL already locked, next console line will be concatenated. If run on a multiple CPUs, you get multiple lines concatenated. Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21mediatek/mt8183: Support gpio eh and rsel setting for I2Cjg_poxu
The setting of these registers are only for i2c pin. BUG=b:80501386 BRANCH=none TEST=Boot correctly on Kukui Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Signed-off-by: jg_poxu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/30974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-21timestamp: Move timestamp_should_run() callKyösti Mälkki
Old location caused spurious error messages when called from APs, where timestamp_add_now() should do nothing. Moving the test also makes get_us_from_boot() usable from APs (assuming cache coherency). Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31524 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21soc/intel/cannonlake: SoC specific microcode update checkRonak Kanabar
For CFL and WHL, Microcode is being loaded from FIT. Both supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootblock and ramstage. Avoid the microcode reload by checking for PRMRR support. CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL CPU die is not based on KBL CPU so skip this check for CNL. BUG=b:124126405 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Reviewed-on: https://review.coreboot.org/c/31492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-21sb/intel/bd82x6x: Fix default IRQ mappingNico Huber
The default mapping was probably copy-pasted from a random board and disabled some interrupts (by implicitly clearing some register bits). We provide a new default mapping with some reasoning, that tries to be most compatible (i.e. avoids to use PIRQ E-H that are not shareable on some boards). The following functions had their interrupt pin disabled before: o SATA 2 (explicitly, no board seems to enable the device) o PCIe Root Port #4, #6-#8 (probably by accident) PIRQs used before this change: A-D, F and H. After this change: A-D. Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31498 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21mb/roda/rk886ex/acpi/superio.asl: Fix copy-paste error on "COMB"Elyes HAOUAS
Error spotted using IASL 20190215: "Object is created temporarily in another method and cannot be accessed" Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21mb/roda/rk9/acpi/superio.asl: Fix copy-paste error on "COMB"Elyes HAOUAS
Error spotted using IASL 20190215: "Object is created temporarily in another method and cannot be accessed" Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21Makefile.inc: Keep .asl intermediatesNico Huber
We used .aml as the file extension for preprocessed ASL code. That file gets overwritten with the compilation results, fix that. Change-Id: I11a03dfbcebb0fd762da7b27862a7bdb9a581b92 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21soc/intel/cannonlake: Add field to identify single channel memoryShelley Chen
Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21src/soc/intel/cannonlake: Add PsysPmax settingGaggery Tsai
This patch feeds PsysPmax setting to FSP through UPD and adds a psys_pmax member in chip information so that we can set PsysPmax through DT. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=None BRANCH=None TEST=Set psys_pmax to an example value eg 101 in DT && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/31505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix. The _DSM method gets injected into DSDT table and called from kernel. LPIT table is hardcoded in this patch but the proper way to implement is to use inject_dsdt to make the _DSM methods available for soc's to implement. Calling the LPIT table from mainboard here so that with the current implementation the platforms which do not have lpit support throw compilation error. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Reviewed-on: https://review.coreboot.org/c/31101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-20Documentation: take the sting out of the requirementsPatrick Georgi
The requirements read a bit as if we only encourage coreboot experts to try to take on these projects. These requirements should be understood as "this is what you'll need to learn", hopefully guiding interested people in picking a project that suits their interests. Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31480 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20Documentation: Add Clang support to project ideasPatrick Georgi
Change-Id: Iaccb5ca5606b83a4b37930b4399ddcf9eddd494b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-20util/lint: Exclude util/inteltool from checkpatchNico Huber
It's causing too much noise during review of register tables. Change-Id: Iae6cd4454c5ed84b5fe0ea5f8a244e2a2fa13407 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31367 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20sb/intel/i82371eb/fadt: Fix compilation on x86_64Patrick Rudolph
Change-Id: I8997910ff003a4d0c97656cb1e9a4342230ac51a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-20drivers/spi/spi_flash.c: Avoid static scan false positiveRichard Spiegel
Static scan-build indicates a possible invalid return from function spi_flash_cmd_erase(). The root cause is because the scan believes it's possible for offset to be above the end address in the first pass, thus not setting a value for variable ret. Assign initial value of -1 to variable ret to make checker happy. BUG=b:112253891 TEST=build grunt Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-20walkcbfs: Only compile on x86_32Patrick Rudolph
The current implementation was designed for x86_32, so don't attempt to compile it on x86_64 until it is fixed. Fixes compilation error on x86_64. Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-20drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 moduleSubrata Banik
Add HrP 9560 module device ID (0x02F0) into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/31475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-20sifive/hifive-unleashed: Drop unneeded console_tx_flush()Kyösti Mälkki
Every printk() call already does console_tx_flush() so there should not be anything in transmit buffer when we return from console_init(). Change-Id: Iff2927c02d2c8031907620a056782bb014f20162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31369 Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet specChris Zhou
After adjustment on Sarien EVT Touch Screen CLK (Elan): 389.7 KHz Touch Screen CLK (Melfas): 377.7 KHz Touch Pad CLK: 385 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope with sarien. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d Reviewed-on: https://review.coreboot.org/c/31476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-19soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Reviewed-on: https://review.coreboot.org/c/31433 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-19Documentation: Add past talks to conferences pagePatrick Georgi
Change-Id: I2b8a0ebda3c8fa7d1777a6f0628fd99d73a0d341 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-18mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1John Su
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/sarien/variants/sarien: Update thermal configuration for DPTFJohn Su
Follow thermal table (b:123383634 comment#1) for EVT1 tunning. BUG=b:123383634 TEST=Built and tested on sarien system Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18soc/intel: Add mem_rank info in SMBIOSFrancois Toguo
"mosys memory spd print all" returns incorrect memory ranks info. This patch and 2 upcomming ones (one in FSP) will address the issue. BUG=b:122329046 TEST=Boot to OS on Bobba variant of Octopus BRANCH=octopus Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842 Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Reviewed-on: https://review.coreboot.org/c/31235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-18soc/intel/skylake: Use real common code for VMX initNico Huber
Use the common VMX implementation, and set IA32_FEATURE_CONTROL lock bit per Kconfig *after* SGX is configured (as SGX also sets bits on the IA32_FEATURE_CONTROL register). As it is now correctly based on a Kconfig, the `VmxEnable` devicetree setting vanishes. Test: build/boot google/[chell,fizz], observe Virtualization enabled under Windows 10 when VMX enabled and lock bit set. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAMDuncan Laurie
The Intel SOC can only shadow the top 16MB of SPI into memory so in order to make it easier to access the NVRAM region with memory mapped interface move it above the much larger RW_LEGACY region. I tested to confirm that this region can now be read via MMIO interface and does not need to use the hwseq SPI controller. Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-02-18mb/google/sarien: Create VR config settingsRoy Mingi Park
Create VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/kahlee: Enable mode change as wake source for S3Mengqi Guo
This change enables mode change as a wake source for S3. BUG=b:124132058 Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184 Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://review.coreboot.org/c/31429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-18src/mainboard/kahlee: Remove delan variantMartin Roth
BUG=b:121354442 TEST=None Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/31424 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18crossgcc: Update MPFR to version 4.0.2Elyes HAOUAS
Change-Id: I5569e61c2a3a64cf353afe3195eca82709362305 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien/variants/arcada: Update thermal configuration for DPTFCasper Chang
Update dptf for arcada EVT. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5 Reviewed-on: https://review.coreboot.org/c/31331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18Documentation: add Skulls to the list of distributionsMartin Kepplinger
There seem to be enough users of the Skulls images to have the project listed in our docs. Change-Id: I5a8f24005fec87d53af7ad53370cb6a704378622 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-18Documentation/lesson1: Update references to compiler packagesNico Huber
Change-Id: Ie9daa70c56552cccfe28e9a4903f87d43221375e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-18mb/google/laser: Disable touch screen device that according to SKU IDpeichao.wang
We need disable touch screen device on laser SKU ID 6. BUG=none TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell): 6, Laser14(clamshell + touch):7) distinguish whether disable touch screen device. Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f Reviewed-on: https://review.coreboot.org/c/31428 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-17Documentation: Add broader payload coverage to project ideasPatrick Georgi
A couple people discussed recently how it's a shame that on some architectures we can bring up a device but then have nothing to do with it afterwards. Having payloads to choose from would help a lot there. Change-Id: Ia66f22947d09afe3076cc2ee12f5b652fe80fc3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-15SMBIOS: Update BIOS Information (Type 0) to version V3.2.0Elyes HAOUAS
Add Extended BIOS ROM Size field. Change-Id: Iec35c8c66210f0ddc07a2ca6f976a1f8fc53037d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-15SMBIOS: Add new MEMORY_{TYPE,TECHNOLOGY,OPERATING} macrosElyes HAOUAS
Change-Id: I4e466614d0a9e8c89f298594a5785af775b22a95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 00:50:05 +0000