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2019-10-22soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBEKane Chen
The previous code actually set SlpS0WithGbeSupport even when GBE is disabled in device tree and could cause power consumption in s0ix. This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport, PchPmSlpS0Vm075VSupport by device tree. SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22soc/nvidia/tegra124: Fix null pointer and logic bugJacob Garber
Commit 680027edf6 fixed a null dereference and logic bug in the tegra210 spi code: soc/nvidia/tegra210: Fix potential NULL pointer dereference Recent Coverity scan indicated potential NULL deference; if either spi->dma_in or spi->dma_out are NULL, the fifo_error() check could dereference a NULL pointer. Also fixed what appears to be a logic bug for the spi->dma_out case, where it was using the todo (count) from spi->dma_in. Coverity is warning about the same problem for tegra124, so apply the same fix there. Also, add braces around a while statement. Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 124183, 124185 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platformsArthur Heymans
This follows the ICH7 datasheets. Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36201 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22mb/lenovo/t410/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. This commit follows up on commit 6752b615 with Change-Id I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for const structures"). Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. This commit follows up on commit 9265f89f with Change-Id I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class"). Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22mb/lenovo/*/acpi: Remove unused include smi.hPeter Lemenkov
Change-Id: I995ef40a04c7705def95c2d5950be940503ee5ab Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-22google/chell: Update ICC_MAX configurationMatt DeVillier
Correct ICC_MAX values per SKL-Y EDS spec. Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration] Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012 Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/593715 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2019-10-22mb/google/drallion: Change touch enable pin default valueEric Lai
Change GPP_B21 default to low. This can prevent power leakage of non-touch sku. BUG=b:142849034 BRANCH=N/A TEST=Measure the power of non-touch sku, check GPP_B21 is 0V. Boot up with touch sku and check touch functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
2019-10-22mb/mainboard/hatch: support Goodix touch panel for AkemiPeichao Wang
Configure enable pin GPP_D9 pull high when active BUG=b:143046441 TEST=build bios and verify touch screen works fine Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186 Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22.gitignore: Add an exception for Kconfig.debugArthur Heymans
Change-Id: I70f19497a2cb1314a1ab18a3da5fd47e40fb57cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-22mb/portwell/m107: Clean up unused Kconfig symbolsArthur Heymans
Change-Id: I9714b197ff0d1af834aa29f96b33809396f0b203 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36196 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22util/inteltool: Add server 5065x CPU model supportMaxim Polyakov
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky Lake, Cascade Lake, Cooper Lake). The cores number for these processors exceeds the limit of 8 cores (it is hardcoded in cpu.c). For this reason, the patch also adds code that determines the number of processor cores at run time. These changes are in accordance with the documentation: [*] pages: 2-265 ... 2-286, 2-297 ... 2-308. Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-10-22mb/google/octopus: Override VBT selection for BloogletTony Huang
Share the same vbt_blooguard.bin to disalbe DRRS support. BUG=b:143045247 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is blooglet. Change-Id: Ia180f265080f801a09f10ce8a8b520c47f218775 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-22Updated AUTHORS file for src/driversMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I446cd267dec2b6c0f7742a6834c7ee950528ad5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/36182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22AUTHORS: Move src/drivers/[l*-v*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22util/chromeos: Don't hide error outputNico Huber
Change-Id: Idf29275575ca7965a0df98dbc8f2b27ab9c5ec4d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-10-22vc/amd/agesa/f16kb: Cast to UINT64 to avoid overflowJoe Moore
Evaluated using 32-bit arithmetic, then used in a context that expects an expression of type UINT64. Cast to UINT64 instead. Change-Id: I4f0aa26e116b47505633897c790ca8e86ea5dc4e Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22vc/amd/agesa/f16kb: Remove redundant value assignmentJoe Moore
Code sets `Status = TRUE` in section of code that can only be reached if `Status == TRUE`. Change-Id: Id9a49476d17a5ca141994b0d5dfc5e5c62a00f0e Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22sb/intel/common/smihandler: Fix compilation on x86_64Patrick Rudolph
Use uintptr_t instead of uint32_t to fix compilation on x86_64. Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36172 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22Documentation: Fix typoPatrick Georgi
Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-22mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to overridetreeMichael Niewöhner
Move USB ports from the common devicetree to the variants' overridetree as they differ at least for X11SSH-TF and X11SSM-F. Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21drivers/intel/fsp2_0: Add ENV_CACHE_AS_RAM check for consumed rangesMarshall Dawson
Rename the freeranges array to better match what they represent, i.e. ranges that are used by the current running program and CAR region that is not unallocated. Skip adding the CAR region if cache-as-RAM is not active. Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/amd/picasso: Add audio processorMarshall Dawson
Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-21mb/intel/kunimitsu: drop support for FSP 1.1Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - drop FSP-1.1-only romstage.c and spd.c TODO: - testing Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/google/glados: port to FSP 2.0Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - switch to using the FSP default VBT TODO: - testing Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/skl/vr_config: Add VR config for SKL-S/H/U/YMaxim Polyakov
Icc/Loadline automatic detection is supported only for FSP2.0 These changes are in accordance with the documentation: [*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'Elyes HAOUAS
Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21Documentation: Add proposal for a comprehensive image assembly stagePatrick Georgi
I originally put up this document for discussion in 2015 (mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX4V2OSXAQC4B2VUENSFZEWRPPOVRH2/) (doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeIc7Vo/edit) It may be time to revisit the way we define our image layouts now that there are new fmap schemes for new vboot uses. The approach outlined in this document may or may not be the right one, but it's something we have, so let's discuss. Compared to the doc, this will * be updated (things changed in the last 3.5 yearws) * integrate feedback to the doc and on the mailing list back then Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21Documentation: Make sure ifdtool/index gets added to toctreeArthur Heymans
Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21Documentation/writing_documentation.md: Fix typoArthur Heymans
Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21soc/mediatek/mt8183: Force DRAM retraining if hotkey pressedYu-Ping Wu
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21soc/mediatek/mt8183: Skip fast calibration in recovery modeYu-Ping Wu
SoC DRAM team suggested always running full calibration mode in recovery mode because it is possible to get unstable memory even if the complex memory test has been passed. Since the recovery mode runs from RO and we only have training data cache for RW, the trained calibration data can't be saved since RO and RW may be running different firmware. Also revised few message to make it more clear for what calibration mode (fast, full, or partial) has been executed. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21mb/google/hatch/var/dratini: Add ELAN touchscreen supportWisley Chen
Add ELAN EKTH6915 USI touchsreen support. BUG=b:139392144 TEST=check touchscreen work, and confirmed power sequence with vendor. Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21Revert "soc/intel/cannonlake: Remove DMA support for PTT"Jeremy Soller
This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c. Reason for revert: Breaks boot on Whiskey Lake-U boards Both System76 and Purism have had memory initialization failures when this patch is applied, with the following error message: Failed to accommodate FSP reserved memory request! An extra 4096 bytes needs to be reserved for the FSP on these systems, and reinstating the PTT reservation does this as expected. PTT is enabled for the System76 galp3-c in the ME configuration, which is why the behaviour is different. Signed-off-by: Jeremy Soller <jeremy@system76.com> CC: Matt DeVillier <matt.devillier@gmail.com> CC: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sc7180: Provide initial SoC supportT Michael Turney
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-21google/poppy: add VBT for nautilus variantMatt DeVillier
Add data.vbt and modify Kconfig appropriately; allows use of FSP/GOP display init. VBT extracted from stock ChromeOS firmware. Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-21purism/librem_bdw: hook up libgfxinitMatt DeVillier
Test: build/boot Librem 13v1, 15v2 with libgfxinit Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36108 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sb/lynxpoint: Fix 'dead increment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Change-Id: I631524b9346647048fe8ea30387553a5b4651f59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21mb/google/hatch/akemi: disable unused devices for AkemiPeichao Wang
Akemi unused devices declare: - I2C #1 gpio_keys - close I2C #3 - close GSPO #1 BUG=b:142800988 TEST=Reboot stress test and suspend stress test, the DUT will be able to working properly Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086 Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/facebook/fbg1701: rename mainboard.h to logo.hWim Vervoorn
Renamed mainboard.h to logo.h as it only contains logo related items. BUG=N/A TEST=tested on fbg1701 Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-20soc/amd/picasso: Increase max APCB images to 5Marshall Dawson
An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20util/amdfwtool: Add holding locations for more APCBsMarshall Dawson
Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20drivers/intel/fsp2_0: Make vbt_get() conditionalMarshall Dawson
Skip calling vbt_get() if FSP is not supposed to run GOP. Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiBV Sowmya
The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since the default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Correct a few GPIO namesMarshall Dawson
Fix a handful of errors that slipped through in 2e0f2788 "soc/amd/picasso: Update GPIO configuration". Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36118 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src/soc/amd/common: Add Azalia support to HDAMarshall Dawson
Let the mainboard decide whether to let coreboot load the verb table. Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35274 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20pci_ids: Add AMD Family 17h ACPMarshall Dawson
Add Picasso's Audio Coprocessor Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36116 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Add cpuid for older deviceMarshall Dawson
Make the driver work with stepping=0. Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35273 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 04:02:01 +0000