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2020-08-17sb/intel/i82801jx: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: Ic661a1339892dad668ad3f9e68cab70bf380505f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44130 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17sb/intel/i82801ix: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: Id6c2c7b474ad8f57294bae67c33b2dd26a6a95ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44129 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17sb/intel/i82801gx: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: I1a5b0b9db0cc3847693934de20b5d27605617637 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44128 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17sb/intel/bd82x6x: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: I1e30dd7b300d7975e7a89fbe1e66aaf7affd1702 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44127 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17sb/intel/lynxpoint: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: Ib4929e3213676056ff3f8116d226fd38132baa28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17device/azalia_device.c: Use <device/azalia_device.h> registersElyes HAOUAS
Change-Id: Ia0ba6c2f76221123acd3c5303b0a018c651f3617 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44125 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17soc/intel/common: Move common HDA registers to <device/azalia_device.h>Elyes HAOUAS
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/dedede/var/magolor: Generate SPD ID for supported partsRen Kuo
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR And also remove the deprecated by cl#43989 https://review.coreboot.org/c/coreboot/+/43989 BUG=None TEST=Build the magolor board Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/tglrvp: Update SPD files for HynixAnil Kumar
- Increase DDR Frquency limit to support data rate 4266 Mbps Bug=None Test=Build and boot on tglrvp hardware; $dmidecode --type 17 reflects memory Speed = 4266 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44149 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/up/squared: Increase MAX_CPUS from 2 to 4Reto Buerki
The board also supports Atom processors, which have four physical cores. Signed-off-by: Reto Buerki <reet@codelabs.ch> Change-Id: I98a3da660052eb7ad2f18b0c7fc0e67a609eac54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-17mb/google/zork: adjust i2c2 data hold time for TPKevin Chiu
current setting got 0.278us which is less than the min 0.3us. increase i2c2 data hold time for TP. BUG=b:163613330 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. data hold time measured by scope: 0.3805us Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17mb/google/volteer: Define stop_gpio for goodix touch screenCaveh Jalali
This applies to the goodix touch screen on both the volteer and volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen "Report_Switch" signal. Goodix defines a 1ms (minimum) delay after stop off. In addition, no longer drive this GPIO high by default as it is now controlled by the kernel through ACPI. BUG=b:153705232 TEST=touch screen still functional on volteer; confirmed timings with scope (VDD, RESET, REPORT_SWITCH) Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-17payloads/seabios: Update stable version to 1.14.0Elyes HAOUAS
see https://seabios.org/Releases Change-Id: I20e57314b867581f41921178ff1ffcbaa50a0843 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-17mb/intel/jasperlake_rvp: Re-organize the FMAP layoutKarthikeyan Ramasubramanian
More space is required in the COREBOOT CBFS to accommodate some features. Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has ~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So adjust the GBB region accordingly and extend the COREBOOT CBFS. BUG=b:162159386 TEST=Build the JSLRVP mainboard. Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7 Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-17sb/intel/lynxpoint/smihandler.c: Remove dead assignmentElyes HAOUAS
Also remove unused 'data'. Change-Id: Icaae8a986cd375e2b67f05883688847e1a174082 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44288 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17drivers/intel/fsp2_0/hand_off_block: Remove dead decrementElyes HAOUAS
Value stored to 'size' is never read. Also drop unused parameter. Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17mb/hp: select TPM and TPM1 for all EliteBook laptopsIru Cai
All the Sandy/Ivy Bridge EliteBook and ProBook laptops currently supported by coreboot and on review all support TPM 1.2 according the maintenance and service guide manuals of these laptops. So select the Kconfig options of TPM and TPM 1.2 and add the entry of it to the common device tree. The device tree C source files of 8460p generated by sconfig before and after this change are compared. All the device nodes still exist with nodes under LPC having different device number. Tested with 2560p, which still works without problems, and the TPM can be detected and used in the system. Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17mainboard: Add HP EliteBook 2560pIru Cai
Most of the code is generated by autoport. The laptop works well under coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel 5.4.39 and 5.6.11. Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17cpu/Makefile.inc: Clean up non-existing directory inclusionArthur Heymans
The Allwinner code has been removed from the master branch for quite some time now. Change-Id: I9e5fd267140c180ae145d12b325cc489725f9ad0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17lib/imd_cbmem.c: Add a helper function to indicate that cbmem is readyArthur Heymans
This can be used in romstage in particular to know if dram is ready. Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dramArthur Heymans
INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controllerFelix Held
BUG=b:162302027 Change-Id: Iff9a09cb59fdc16be8b4ea41303704166a97172e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS
Change-Id: I2da586abf63517a2e9b73ea4d3fab513370947bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17drivers/usb: Replace return value -10 with variableJohn Zhao
Coverity detects that value assigned to variable "ret" is overwritten before it is used. Fix the issue by returning right value. Found-by: Coverity CID 1255942, 1241836 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17x4x boards: Remove unused/deprecated cmos bitsArthur Heymans
Receiver enable results are now saved in flash. Change-Id: Ib1a985147b081860c58d1649c4e50301b8144b0c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17cpu/intel/model_6fx: Include Conroe-L microcodeArthur Heymans
This CPU variant has a different CPUID signature. Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17libpayload/defconfig: Set default heap size to 1MiBNico Huber
libpayload's drivers keep growing. With certain hardware/payload combinations (last time witnessed with Kontron/bSL6 and FILO), the default configuration runs out of memory. As there is a lot enabled by default, also set a big default heap size. Tested with FILO on QEMU/Q35. Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-17soc/intel/skylake: Call mainboard ACPI sleep methodsBenjamin Doron
Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17soc/intel/jasperlake: Add IGD Device IDKrishna Prasad Bhat
Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44000 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDurV Sowmya
This patch updates the SLP_Sx assertion widths and power cycle duration for the Japerlake RVP. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on JSLRVP. Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-17mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDurV Sowmya
This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo. Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-17soc/intel/jasperlake: Add FSP UPDs for minimum assertion widthsV Sowmya
Add the FSP UPDs for the chipset minimum assertion widths and Power cycle duration to the chip options which can be configured per mainboard. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159104150 Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-17soc/mediatek/mt8192: Initialize watch dog in bootblockCK Hu
Initialize watch dog so the system won't reboot on timeout. In addition, print the reason of reboot triggered by watch dog. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-17soc/mediatek/mt8192: Initialize mmu in bootblockCK Hu
Initialize CPU mmu and config range. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-15mb: remove unnecessary FADT flag devicetree entries for PicassoFelix Held
Those flags already get unconditionally set in soc/amd/picasso/acpi.c. Change-Id: I978c7d67480499d92c193d5bb87bc876211187db Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-15soc/amd/picasso: use FADT devicetree configuration optionsMartin Roth
Two of the items in the FADT ACPI table frequently are partially board- specific, so let's make it easy to update them via devicetree settings. - fadt_boot_arch 0="legacy free" which while reasonable, probably isn't what will be wanted by most mainboards, so this should generally get updated in the specific devicetree. - In fadt_flags all chipset-specific flags get set while the mainboard has to set all other flags that it needs to have set. This patch changes the default for fadt_boot_arch. Change-Id: I6e8d0c60cadfdd24b6926703b252abbc56d436de Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15device/pci_rom.c: Treat BASE_DISPLAY class as GPUBenjamin Doron
The DISPLAY_3D class is for graphics devices that are not connected to displays. This includes GPUs implementing muxless Nvidia Optimus. According to CB:31502, some AMD GPUs are identified as DISPLAY_OTHER. Therefore, consider the entire DISPLAY class as GPUs. Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KBRavi Sarawadi
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 3KB to 5KB to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. Bug=None Branch=None Test=Boot Delbin and check 'cbmem -c | more' for full log message. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Id2ea64feb92ec29df5402b2fb1bac3ff73cc5bb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/intel/skylake: Refactor PEG configurationFelix Singer
Simplify some if-blocks which are used for the configuration, enablement and disablement of the PEG devices. This changes the logic of the code, since it configures PegxEnable before the if-blocks, where x is the number of the PEG device, and the further configuration of the PEG devices depends on the enablement of PegxEnable. Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Factor out unnecessary if-else-blockFelix Singer
Move InternalGfx config option out of the if-else-block and replace the left over config option IgdDvmt50PreAlloc by a ternary expression. Also, adjust related code comments to fit the new logic of this code. This changes the logic of the code, since InternalGfx is configured first and IgdDvmt50PreAlloc depends on its value. The negation in the ternary expression is removed to improve the readability. Change-Id: I89ff17f4574a7ade228c1791f17ea072fb731775 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Use PEG definitions from pci_devs.hFelix Singer
Change-Id: I7114deed35f25e74ac508f08e9c85653a7fe39ed Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Add PEG device definitions to pci_devs.hFelix Singer
Change-Id: Ib2453425f44e2b4abd5566f454ae68b704dbc33e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14cpu/qemu-x86: Fix timestamp and bist reportingPatrick Rudolph
Change-Id: Id66a7f6767735862e138c58c4bcc9e68215dd3c5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-14arch/x86/postcar: Add x86_64 supportPatrick Rudolph
* Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14mb/google/volteer: Only enable TBT root ports if USB4 is supportedBrandon Breitenstein
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if the DB doesn't support USB4 the platform as a whole should only be USB3 capable and TBT functionality on both ports should not be enabled. BUG=NONE BRANCH=NONE TEST=Built coreboot and verified that TBT was disabled on platform with USB3 DB and enabled on platform with USB4/TBT DB Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-14soc/amd/picasso/acpi: Set missing RTC offsetsRaul E Rangel
The RTC Date Alarm and RTC AltCentury fields are supported on picasso. These get consumed by the linux kernel: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/rtc/rtc-cmos.c;l=1243 BUG=b:160277722 TEST=Boot kernel and make sure suspend stress test works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie83d7e0a06107a6de095f3e4c521d91e90920c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-14mb/google/dedede: Add a board specific resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. Request Embedded Controller (EC) to perform AP reset so that TPM can detect that event. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when CSE Lite jumps from RO to RW with an older and newer Cr50 firmware. Cq-Depend: chromium:2337430 Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-14mb/ocp/deltalake: enable VT-dJonathan Zhang
Update devicetree.cb to configure VT-d to be enabled. TESTED=booted on DeltaLake config A server, and verify DMAR table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7d76cd9d50d3e69a4919de281f11d30851bffa3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14soc/intel/xeon_sp/cpx: add VT-d supportJonathan Zhang
Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 23:18:14 +0000