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2016-06-28tint: Fix tint and add Kconfig optionAntonello Dettori
Fix the compiler errors with tint, improves the Makefile, adds Kconfig integration and secondary payload option. Change-Id: Ia99e30f566d5ccf0d083e52bf174970535daefc5 Signed-off-by: Antonello Dettori <dettori.an@gmail.com> Reviewed-on: https://review.coreboot.org/14989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-28tegra124: Actually align the framebuffer's bytes-per-line to 32Paul Kocialkowski
The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact@paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14816 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-28google/reef: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325, chrome-os-partner:54581 TEST=device off in devicetree should disable the device. Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28soc/apollolake: Populate fields in FADT to enable\disable SCIHannah Williams
This will allow kernel to trigger a APM SMI to enable\disable SCI Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27intel/amenia: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I486a4c5e8970047477068e22b799d06caea03330 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15338 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27soc/intel/apollolake: add code to disable unused deviceJagadish Krishnamoorthy
Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27intel/apollolake: Set sleep type to S5 on vboot reboot requestFurquan Shaikh
Add support for vboot_platform_prepare_reboot which is called whenever vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in such conditions since the platform would no longer be in a resuming state after reset. Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15340 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-26intel/nehalem: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: Ic82a732ba28ba24e42a635539cca3d76128b40b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-26intel/gm45: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I3148dbbcb06676f48b6bc357124403b70b9bcb6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15246 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I6f0cdc80870fddeaada3191e493bd85fdefee07f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-26ifwitool: Fix gcc error due to shadowed global declarationWerner Zeh
The name 'bpdt_size' is used for a function as well as ia local variable. As ifwitool is compiled using HOSTCC, there can be an older gcc version used for the compilation. With gcc version 4.4.7 I get the following error: declaration of 'bpdt_size' shadows a global declaration To fix it, rename the function to get_bpdt_size so that names are unique now. Change-Id: I47791c705ac4ab28307c52b86940a7a14a5cfef8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15343 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24rockchip/rk3399: provide multiple SDRAM configurationsLin Huang
We want to be able to easily change SDRAM clock rate for debugging purposes. This patch adds configurations for 4 different clock rates. Same configs are used for all rk3399 boards at 200, 666 and 800 MHz. Kevin board does not run reliably at 666 MHz, an option for it is added to run at 300 MHz, this option is available to Kevin only. There is not much room left in the coreboot romstage section, this is why the config file for 928 MHz is being added with this patch but is not included in the code, one of the lower frequency options will have to be dropped for the higher frequency option to be added. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and gru. Verified that on Kevin the firmware reports starting up SDRAM at 300 MHz and on Gru at 800 MHz. Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1 Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353493 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15309 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24rk3399: clean up sdram controller initialization codeVadim Bendebury
This is a purely cosmetic change replacing some of the more prominent copy and paste sections of the code with compressed versions of the same. BRANCH=none BUG=none TEST=with the rest of the patches applied stressapptest still runs for an hour on both Kevin and Gru. Change-Id: I492e1898e312473d07d9e5eceb3e3e10b48ee35f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb8043f96457d090dbbee57097bc1d685e7d32d2 Original-Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353774 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15308 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add elog supportSimon Glass
Add code to start up elog. This uses the EC RTC to obtain the timestamp. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages Change-Id: I4971d661b267ae8b7e3befeff482ca703b741743 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e4e9823d8cecbf9873e78b048e389c7a737ff512 Original-Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353822 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15306 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add get_developer_mode_switch()Simon Glass
Add this function and make it return 0, as there is no physical dev switch (at least I think this is what we are supposed to do). This is needed for elog to work, which is needed so we can test RTC properly. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages: elog_init() SF: Detected W25Q64 with sector size 0x1000, total 0x800000 elog_find_flash() FMAP: area RW_ELOG found @ 5d8000 (32768 bytes) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) ELOG: flash area invalid elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096) SF: Successfully erased 4096 bytes @ 0x5d8000 elog_prepare_empty() elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) elog_is_header_valid() elog_update_event_buffer_state() elog_is_buffer_clear(base=0x000000000031d670 size=4088) elog_is_area_valid() ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 elog_add_event_raw(type=16) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11) ELOG: Event(16) added with size 11 elog_add_event_raw(type=17) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13) ELOG: Event(17) added with size 13 elog_add_event_raw(type=A0) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9) ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot I can't actually see the timestamp, but the EC traffic is visible. Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353821 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15305 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Show the current time on start-upSimon Glass
Display the current time from the EC. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I4288efc56f00e47f7575d0379a44871351da6200 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d0361193e0ec135e21f0611d7fa6e5c02f2b2bfc Original-Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351783 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Enable EC-based RTCSimon Glass
Obtain the real-time clock value from the EC on start-up and show the current time. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and EC clock set, boot on gru into Linux shell and check the firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:09:16 Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351781 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15303 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24soc/apollolake: Clear SLP_TYP in PM1_CNTHannah Williams
Change-Id: Id49319ec6b52648b03eaeddfdd1580dd82110fb9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Add handling of global reset in FspNotify stageAndrey Petrov
Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24drivers/intel/fsp2_0: Add simple reset handlerAndrey Petrov
Any FSP API call may request a reset. This is indicated in API function return code. Add trivial reset handler code. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: Ieb5e2d52ffdaf3c3ed416603f6dbb4f9c25a1a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Implement global reset handlingAndrey Petrov
Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Move PMC BAR setup to bootblockAndrey Petrov
Some features of PMC needs to be accessed before romstage. Hence, move PMC BARs setup into bootblock. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15332 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Add utility functions for global resetAndrey Petrov
Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/common: Add prototype for global_reset() resetAndrey Petrov
Add prototype for global_reset() that some SoCs need to provide. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I8afe076b6f4f675b3c6a3ec0e4dd69f950baa4ef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15333 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24Revert "intel/apollolake: Use custom reset calls"Andrey Petrov
Looks like we need to do real cold reset in some FSP flows, so reverting this. This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d. Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15331 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24ec/google: Add support for the EC 'get time' functionSimon Glass
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to implement rtc_get() so that this can be plumbed in. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits, boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505 Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351780 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24lib: Add real-time-clock functionsSimon Glass
Add functions to convert between seconds and a struct rtc_time. Also add a function that can display the time on the console. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and after setting RTC on the EC: boot on gru into linux shell, check firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:44 Then reboot ~10 seconds and check again: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:54 Change-Id: Id148ccb7a18a05865b903307358666ff6c7b4a3d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b02dbcd7d9023ce0acabebcf904e70007428d27 Original-Change-Id: I344c385e2e4cb995d3a374025c205f01c38b660d Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351782 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24intel/kunimitsu: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tesed on a Chell mainboard since I lack a kunitmisu device. I used different GPIOs across boots to verify that the different audio codec devices would be "detected" and generated in the SSDT. Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15317 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/lars: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tested on a Chell mainboard since I lack a lars device. Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15316 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/glados: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified on a glados board by verifying the SSDT contents against what used to be in the DSDT. Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/chell: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified by comparing the generated ACPI code in the SSDT to what was in mainboard.asl and ensuring the contents are functionally equivalent. Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24soc/intel/apollolake: Include _PTS, _WAK and _SWSHannah Williams
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-24src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copyBenjamin Barenblat
Rewrite inline assembly for ARMv7+ to correctly annotate inputs and outputs. On ARM GCC 6.1.1, this causes assembly output to change from the incorrect @ r0 is allocated to hold dst and x0 @ r1 is allocated to hold src and x1 ldr r0, [r1] @ clobbers dst! ldr r1, [r1, #4] str r0, [r0] str r1, [r0, #4] to the correct @ r0 is allocated to hold dst @ r1 is allocated to hold src and x1 @ r3 is allocated to hold x0 ldr r3, [r1] ldr r1, [r1, #4] str r3, [r0] str r1, [r0, #4] Also modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. Change-Id: I255995f5e0a7b1a95375258755a93972c51d79b8 Signed-off-by: Benjamin Barenblat <bbaren@google.com> Reviewed-on: https://review.coreboot.org/15216 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24arch/x86/smbios: Correct manufacturer IDElyes HAOUAS
Correct standard manufacturer's identification code. Change-Id: I273711e121a61a91176c15cd4cab75420f1f5a39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15271 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-24SPD: Add DRAM devices typesElyes HAOUAS
Add SDRAM or module types to byte 2. Change-Id: Id6e654a3a714c164bc9a7fbd9ab3e2f3c44ca5ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15265 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix DDR3 SDRAM memory module typesElyes HAOUAS
Correct the definitions for 16b and 32b SO-DIMM modules. Regarding JEDEC Standard No. 21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules (2014), the hex values used for 16b-SO-DIMM is 0x0c and for 32b-SO-DIMM module type is 0x0d Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15262 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix and add DDR2 SDRAM memory module typesElyes HAOUAS
Correct the definitions and add 72b-SO-CDIMM and 72b-SO-RDIMM Change-Id: I33532e30f45f6c8c0eb6d47b0bea87689d2d9a1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15204 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24spd: Add module voltage for 1.8VElyes HAOUAS
Add SSTL 1.8 V Interface Level as specified in JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10. Change-Id: I0112a85f557826b629109e212dbbc752aeda305d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-23intel/apollolake: Enable prefetching and caching for BIOS readsFurquan Shaikh
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15321 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23samsung/lumpy: Fix build with System Agent blobKyösti Mälkki
Broken with commit: 2585209 mb/samsung/lumpy/romstage: read SPD data of removable DIMM The blob can pick SPDs from the addresses defined in pei_data and we do only define read_spd() with USE_NATIVE_RAMINIT. Change-Id: Ibd6d7a4a53fa808b476d3060872cb10d3dfce534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15329 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23google/reef: Update chromeos.fmd fileFurquan Shaikh
1. Mark 256KiB at end of BIOS region as unusable BIOS region is memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it accordingly in fmd file. 2. Use up holes in RW region for RW_A and RW_B. 3. Fill up holes in RO with UNUSED regions. BUG=chrome-os-partner:54672 Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15313 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA valueLin Huang
for per cs training, there should be more cycles to switch delay line. so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/352953 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rockchip/rk3399: fix sdram training issueLin Huang
After write leveling for all ranks, check the PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or (0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write leveling again. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4 Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351825 Reviewed-on: https://review.coreboot.org/15300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23kconfig: add missing SPI TPM CS config definitionVadim Bendebury
To fully define TPM attachment to a SPI interface both bus and CS (chip select) settings are required. Add the missing CS configuration option. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied it is possible to compile in and run TPM2 SPI driver. Change-Id: If297df8e5b9526f156ed1414eb9db317d6af5b33 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353913 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15299 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23tpm2: add SPI TPM driverVadim Bendebury
This introduces a SPI TPM driver compliant with the TCG issued "TPM Profile (PTP) Specification Revision 00.43" which can be found by googling its title. The driver implements both the hardware flow control protocol and the TPM state machine. The hardware flow control allows to map SPI based TPM devices to the LPC address space on x86 platforms, on all other platforms it needs to be implemented in the driver software. The tis layer is somewhat superficial, it might have to be expanded later. A lot more implementation details can be found in the code comments. Also, it is worth mentioning that this is not a complete version of the driver: its robustness needs to be improved, delay loops need to be bound, error conditions need to propagate up the call stack. BRANCH=none BUG=chrome-os-partner:52132, chrome-os-partner:50645, chrome-os-partner:54141 TEST=with the rest of the patches applied coreboot is able complete Chrome OS factory initialization of the TPM2 device. Change-Id: I967bc5c689f6e6f345755f08cb088ad37abd5d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5611c6f7d7fe6d37da668f337f0e70263913d63e Original-Change-Id: I17d732e66bd231c2289ec289994dd819c6276855 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/350124 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15298 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Tested-by: build bot (Jenkins)
2016-06-23rockchip/rk3399: Clean up voltage rail settingsLin Huang
The CENTER LOGIC should always be 0.9V and can not be adjusted, so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now DDR seems to run stable at 800MHz on the gru board. BRANCH=none BUG=chrome-os-partner:54144, chrome-os-partner:53208 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478 Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/352772 Reviewed-on: https://review.coreboot.org/15297 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23gru: kevin: initialize cr50 SPI interfaceVadim Bendebury
Set up the pins and initialize the driver. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the cr50. Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349852 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15296 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rk3399: add definition for SP0 iomuxVadim Bendebury
This register is described in the TRM in section called GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0 interface. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate over SPI0 Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349851 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15295 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 13:58:06 +0000