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2015-11-22drivers/ti/tps65913: Set default values in KconfigMartin Roth
Set default values for the hex and int kconfig symbols so they don't come up as undefined. Change-Id: Ib51272f35baa32fe5f3dc369c7f554c77bc2add1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12499 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-11-22drivers/ams: Set default values in KconfigMartin Roth
Set default values for the hex and int kconfig symbols so they don't come up as undefined. Change-Id: If104cbf7d84719a63fb80aa955efa8baa3953d09 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12498 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-11-21coreinfo: Rewrite bootlog_moduleYasha Cherikovsky
The old bootlog_module implementation was completely broken: - It assumed that the console buffer is located at address 0x90000, and of size 64K. It is not correct nowadays. - It displayed the buffer in a very hacky way, the code was riddled with TODOs and FIXMEs. Scrolling had sometimes unexpected behavior. The new implementation: - Uses the cbmem console as the source of data. It takes the console information from lib_sysinfo of libpayload, which is constructed from the coreboot tables (no more hardcoded adressess). - Properly sanitizes the console buffer for display, which makes scolling and display much easier to implement. Change-Id: I3f87ec920631da2acfd3f52273228703f22f469f Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com> Reviewed-on: http://review.coreboot.org/12440 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21build system: also remove .xcompile.tmpPatrick Georgi
Change-Id: I18df6a6ec088b9036c3c17480843e5710bc82308 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12502 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21MAINTAINERS: Add myself to a few itemsMartin Roth
Change-Id: I407cee76cf1eb695732ad54287831a151a8ae3f5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12491 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-21console: Add help for serial IO port selectionMartin Roth
Add help and a comment about the serial IO port selection to give the user better feedback when a port index is selected. Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12487 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-21hexdump: Fix output if length is not a multiple of 16Ben Gardner
hexdump currently rounds up length to a multiple of 16. So, hexdump(ptr, 12) prints 16 hex digits, including 4 garbage bytes. That isn't desirable and is easy to fix. Change-Id: I86415fa9bc6cdc84b111e5e1968e39f570f294d9 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12486 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21baytrail: add C0 and D0 stepping decodeBen Gardner
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11. Add that so the debug log shows 'D0' instead of '??'. Also, add the C0 stepping decode to fsp_baytrail. Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21cpu/amd/car/post_cache_as_ram: Avoid trailing spacesPaul Menzel
Looking at the coreboot console logs there are sometimes trailing whitespaces in the output, for example, if writing `Done` was not possible. Adapt the code, that spaces are only added when needed. Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12357 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21chromeos: Fix Kconfig TPM warnings on systems with no LPC TPMMartin Roth
Put dependecies on CHROMEOS's selection of the Kconfig symbols TPM_INIT_FAILURE_IS_FATAL and SKIP_TPM_STARTUP_ON_NORMAL_BOOT to match the dependencies on those symbols where they are defined in src/drivers/pc80/tpm/Kconfig The file that uses these only gets built in if CONFIG_LPC_TPM is selected selected. The warnings were: warning: (CHROMEOS) selects TPM_INIT_FAILURE_IS_FATAL which has unmet direct dependencies (PC80_SYSTEM && LPC_TPM) warning: (CHROMEOS) selects SKIP_TPM_STARTUP_ON_NORMAL_BOOT which has unmet direct dependencies (PC80_SYSTEM && LPC_TPM) Change-Id: I7af00c79050bf511758bf29e3d57f6ff34d2a296 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12497 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-21amd/family_10h-family_15h: Fix poor performance on Family 15h CPUsTimothy Pearson
Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12028 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-21mainboard/asus/kgpe-d16: Update NB VDD upper voltage limitTimothy Pearson
Certain older Opteron processors use a higher (+1.2V) northbridge voltage. The existing code assumed the use of +1.1V northbridge voltages and threw an alert when the older Opterons were installed. Update the permissible NB voltage range to include both the 1.1V and 1.2V Opteron processors. Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20northbridge/amd/amdht: Add comment for HT Freq write orderingTimothy Pearson
The BKDG is not correct regarding HT Freq write ordering; indicate this in a comment to avoid confusion. Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12030 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20cpu/amd/family_10h-family_15h: Fix incorrect revision detectionTimothy Pearson
The revision detection code for AMD Family 10h/15h was modified to use a 64-bit value instead of 32-bit in order to accomodate additional processor revisions. The FIDVID code was not updated at that point, leading to incorrect revision use during FIDVID. Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12026 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20x86emu: Remove XFree86 CVS tagsStefan Reinauer
They're not supported by git. Change-Id: I8157cdc0f5f4072af588772680741b72d21a9223 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12494 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20x86emu: Undefine _NO_INLINEStefan Reinauer
Never defined by the server. Change-Id: If22727cf3953c2931d107146fb99b5997f8a13d5 Original-Reviewed-by: Eric Anholt <eric@anholt.net> Original-Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12493 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20x86emu: Fix some set-but-not-used warnings.Stefan Reinauer
Change-Id: Ide861733d721a21b77862076bf7ad70c7ee6a472 Original-Reviewed-by: Adam Jackson <ajax@redhat.com> Original-Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12021 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20intel/skylake: Fix flash_controller.c compilationStefan Reinauer
Since this code is not currently being built by coreboot, it failed compilation. Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12466 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20rules.h: Add ENV_STRING and use it in console_init()Ben Gardner
Move the #ifdef chain to set the stage name to rules.h. Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12479 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20google/veyron_mickey: Update LPDDR3 configurationjiazi Yang
This makes the same changes to the LPDDR3 configuration that were made for Samsung modules: - Enable ODT function - Change DS to 40 from 34.3 BUG=chrome-os-partner:47416 BRANCH=firmware-veyron-6588.B TEST=Boot on mickey elpida board Change-Id: If8c729188803dd854dbbe80539fb228636b5eb9f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3eb8bc31b9727b67a6b53b4370315010d9d6379 Original-Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1 Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311153 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311855 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12484 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20util/mma: Add MMA scripts for setup and getting resultsPratik Prajapati
mma_setup_test.sh is used to set MMA test name and MMA test config name. After executing this script user needs to reboot the system and FSP/coreboot would execute the selected MMA test. FSP and coreboot needs to be built with MMA support. mma_get_result.sh will get the raw MMA results from cbtable and save it to bin file. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3). CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: Ie330151535809676167f0b22c504a71975841414 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35469218fe53c1ac211f55bd26a206a05a827453 Original-Change-Id: I7d20aca63982e13edc41be2726f3cc7e41d95bae Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299473 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12483 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20util/cbmem: Add --rawdump <cbtable ID> and extend -l outputPratik Prajapati
Changed following things, (1) cbmem -l would give both ID and Name for coreboot table along with START and LENGTH of each entry e.g. localhost ~ # cbmem -l CBMEM table of contents: NAME ID START LENGTH <.....> 3. TIME STAMP 54494d45 77ddd000 000002e0 4. MRC DATA 4d524344 77ddb000 00001880 5. ROMSTG STCK 90357ac4 77dd6000 00005000 6. VBOOT WORK 78007343 77dd2000 00004000 7. VBOOT 780074f0 77dd1000 00000c3c 8. RAMSTAGE 9a357a9e 77d13000 000be000 9. REFCODE 04efc0de 77c01000 00112000 10. ACPI GNVS 474e5653 77c00000 00001000 11. SMM BACKUP 07e9acee 77bf0000 00010000 <..etc..> (2) With this patch, new command line arg "rawdump" or "-r" will be added to cbmem user can grab the ID with "cbmem -l" and execute "cbmem -r <ID>" to get raw dump of cbtable for the <ID> in interest. This change is needed to get MMA results data from cbtable. Coreboot stores the MMA results in cbmem. Separate post processing scripts uses cbmem utility to get the these data. This feature in the cbmem tool can also help debugging some issues where some specific ID of cbtable needs examination. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3). Cbmem -r and -l works as described. Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I70ba148113b4e918646b99997a9074300a9c7876 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f60c79d845d4d4afca480b6884c564a0d5e5caf8 Original-Change-Id: I1dde50856f0aa8d4cdd3ecf013bd58d37d76eb72 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299474 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12482 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20intel: Add MMA feature in corebootPratik Prajapati
This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20cbfstool: Add EFI and MMA file typesPratik Prajapati
Add efi and mma file types. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3). cbfstool shows mma and efi file types. Not tested on Glados CQ-DEPEND=CL:299476,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I4f24a8426028428d613eb875c11cca70d9461dd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c625ad2aeca3a9358fba1eb7434c66ff991131a Original-Change-Id: I611819d213d87fbbb20816fdfb9e4b1401b3b89b Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299475 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12480 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20util/cbmem: Fix out of bounds accessAaron Durbin
Building cbmem with ASan $ CC=gcc-5 CFLAGS="-O1 -g -fsanitize=address -fno-omit-frame-pointer" LDFLAGS="-fsanitize=address" make it sometimes finds a heap-buffer-overflow, while dumping the CBMEM console. $ sudo ./cbmem -c ================================================================= ==11208==ERROR: AddressSanitizer: heap-buffer-overflow on address 0xb5d5782b at pc 0x0804a4d7 bp 0xbfe23bc8 sp 0xbfe23bbc WRITE of size 1 at 0xb5d5782b thread T0 #0 0x804a4d6 in dump_console /home/joey/src/coreboot/util/cbmem/cbmem.c:553 #1 0x804a4d6 in main /home/joey/src/coreboot/util/cbmem/cbmem.c:1134 #2 0xb70a3a62 in __libc_start_main (/lib/i386-linux-gnu/i686/cmov/libc.so.6+0x19a62) #3 0x8048cf0 (/home/joey/src/coreboot/util/cbmem/cbmem+0x8048cf0) 0xb5d5782b is located 50 bytes to the right of 131065-byte region [0xb5d37800,0xb5d577f9) allocated by thread T0 here: #0 0xb72c64ce in __interceptor_malloc (/usr/lib/i386-linux-gnu/libasan.so.2+0x924ce) #1 0x804a407 in dump_console /home/joey/src/coreboot/util/cbmem/cbmem.c:542 #2 0x804a407 in main /home/joey/src/coreboot/util/cbmem/cbmem.c:1134 #3 0xb70a3a62 in __libc_start_main (/lib/i386-linux-gnu/i686/cmov/libc.so.6+0x19a62) SUMMARY: AddressSanitizer: heap-buffer-overflow /home/joey/src/coreboot/util/cbmem/cbmem.c:553 dump_console Shadow bytes around the buggy address: 0x36baaeb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x36baaec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x36baaed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x36baaee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x36baaef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 =>0x36baaf00: fa fa fa fa fa[fa]fa fa fa fa fa fa fa fa fa fa 0x36baaf10: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x36baaf20: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x36baaf30: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x36baaf40: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x36baaf50: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Heap right redzone: fb Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack partial redzone: f4 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe ==11208==ABORTING Fix up commit 06b13a37 (cbmem: Terminate the cbmem console at the cursor position.) by reverting setting the cursor to 0. Change-Id: Id614a8e0f1a202671dd091f825d826a17176bfcc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20southbridge/amd: add support for Bolton FCHFelix Held
The Bolton FCH needs different firmware files than the Hudson FCH. A small patch to vendorcode is probably needed to make the XHCI controller work. XHCI_DEVID in pci_devs.h is probably wrong for Hudson. Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/9623 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20cpu/amd/fam10h-fam15h: Set northbridge throttle valuesTimothy Pearson
The existing code did not set the northbridge throttle values on Family 15h, leading to sporadic and random deadlocks in the crossbar per AMD notes. Properly set the northbridge throttle values on Family 15h. Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12025 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-20libpayload: PDCurses: Remove trailing whitespaceStefan Reinauer
find . -type f |xargs perl -pi -e 's, *$,,' find . -type f |xargs perl -pi -e 's, *$,,' Change-Id: I62c2bc15b7c395a68b68422e701edf98b08e27c6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-20siemens/mc_tcu3: Clear checksums in hwinfoWerner Zeh
Clear the precomputed checksums in hwinfo as they will be updated in manufacturing process. Change-Id: I952ca8f1ca32831c4b296de633c0d58da111ccba Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/12475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20build system: tighten down .xcompile handling some morePatrick Georgi
Bail out if .xcompile is incomplete or can't be regenerated. Change-Id: I74adeded7a3e849b25bf65c5b02f67820f29c7e2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12477 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20build system: don't let a broken .xcompile linger in the treePatrick Georgi
If the xcompile script fails (with an error message), we should delete the generated file so that later builds try to regenerate the file and re-report the problem if it still persists. Change-Id: I70ec37ca8ccb8ed3d8d0da48b326f5e0d722f314 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12473 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20AMD Bettong: add READMEWANG Siyuan
This is the initial version of README. AMD provides stable Bettong code in github. Add the link and bug fixed list to README. Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11737 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20AMD Bettong: refactor PCI interrupt tableWANG Siyuan
1. Use write_pci_int_table to write registers 0xC00/0xC01. 2. Add GPIO, I2C and UART interrupt according "BKDG for AMD Family 15h Models 60h-6Fh Processors", 50742 Rev 3.01 - July 17, 2015 3. The interrupt valudes are moved from bettong/mptable.c. All devices work in Windows 10. Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11746 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20Makefile: Set HOSTCC as gcc or cc respectivelyzbao
The HOSTCC should be set in .xcompile, which tests the existence of gcc and cc. But the .xcompile has to be included after kconfig/Makefile. So building util/kconfig uses the seperated HOSTCC definition above it, instead of the one in .xcompile. For the system which clang is the default host compiler, gcc is not installed by default. In that case, we need to set HOSTCC as cc. Change-Id: I1e51a37c4426e2c97d36a31f26a18ab4b0d0608d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12331 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20xcompile: Redirect the objdump stderr to /dev/nullzbao
On system with clang, "as" is available but "objdump" is not by default. So if ${gccprefix} is empty, "as" can run successfully and the "objdump" below might report error. Mask that output. Change-Id: I9940f069f66e097973ed6138cf3c696087fa5531 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11681 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20util/kconfig: Set parameter of mkdir to only one for mingw.zbao
The second parameter is to set file permissions for the directory, which is not needed in mingw. Change-Id: I88e317f075e8a39f0a280b3dd6e597d119f0f741 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11723 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20cbfstool: Fix build error with clang when comparing enumzbao
If HOSTCC=clang, the -Wtautological-constant-out-of-range-compare is set automaticaaly. That assume the value of type enum is in the defined range. Then testing if a type enum is out of range causes build error. Error: coreboot/util/cbfstool/cbfs_image.c:1387:16: error: comparison of constant 4 with expression of type 'enum vb2_hash_algorithm' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (hash_type >= CBFS_NUM_SUPPORTED_HASHES) ~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. clang version: FreeBSD clang version 3.4.1 (tags/RELEASE_34/dot1-final 208032) 20140512 Target: x86_64-unknown-freebsd10.2 Thread model: posix Change-Id: I3e1722bf6f9553793a9f0c7f4e790706b6938522 Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12330 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20google/veyron_danger & veyron_emile: Fix Kconfig warningsMartin Roth
These platforms needed to be adjusted to fix various Kconfig warnings. Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting MAINBOARD_DO_NATIVE_VGA_INIT. veyron_emile needed a few symbols that depend on CHROMEOS to be moved into a new config CHROMEOS section. This matches the other CHROMEOS platforms. veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the CHROMEOS symbol was set. Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12462 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-20google/lars & intel/kunimitsu: Fix Kconfig warningsMartin Roth
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section. This fixes the kconfig warning: warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects EC_SOFTWARE_SYNC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE) Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12460 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19nb/intel/sandybridge/raminit: Factor out code into toggle_io_resetPatrick Rudolph
Found while doing code review. Use a function to toggle IO reset signal. Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/11916 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19vendorcode/google/chromeos: Cache VPD data into CBMEMHung-Te Lin
There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12453 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-19edid: Don't half parse (and wrongly print) more detailed timingsDouglas Anderson
The EDID parsing code continued to update _some_ fields of the output edid but not others if "did_detailed_timing" was already set. It also then went on to print out this halfway mix of modes each time, despite the fact that it didn't really update everything. Let's fix that. We'll reduce code changes by using a temporary copy of data in detailed_block() and then we'll copy it back if we decide we should update. BRANCH=none BUG=chrome-os-partner:46998 TEST=No more bogus printouts Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9 Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309541 Original-Reviewed-on: https://chromium-review.googlesource.com/309609 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Use a better mode for 640x480Douglas Anderson
The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid clock to use, but is quite hard to make a non-jittery clock from PLLs. It's much easier to make 25.200 MHz, so let's do that. The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia monitor works, so do others Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309540 Original-Reviewed-by: Stphane Marchesin <marcheu@chromium.org> Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532) Original-Reviewed-on: https://chromium-review.googlesource.com/309576 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Don't set standard timings as supported if they're notDouglas Anderson
The set to say that a standard timing was supported was not properly in the "if" test. That meant that even when standard timings weren't supported, we thought that they were. That had the side effect of never using the detailed mode. BRANCH=none BUG=chrome-os-partner:46998 TEST=Adafruit panel works now Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849 Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309521 Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c) Original-Reviewed-on: https://chromium-review.googlesource.com/309552 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12442 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Remove useless parameter from detailed_cvt_descriptor()Douglas Anderson
The detailed_cvt_descriptor() function takes a parameter "out" for no good reason. Remove it. BRANCH=none BUG=chrome-os-partner:46998 TEST=Build and boot Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309598 Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388) Original-Reviewed-on: https://chromium-review.googlesource.com/309496 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12441 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19romcc: Allow adding non-existent paths to include pathStefan Reinauer
This models gcc's (and other compilers') behavior to not bail out with an error when one of the include paths does not exist. Change-Id: Ic93a55cea6b32516fd76da9b49abe7b990829889 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-19mainboard/asus/kgpe-d16: Fix I/O link detectionTimothy Pearson
Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12024 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 01:07:06 +0000