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2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-06payloads/external/SeaBIOS: Bump version to 1.10.1Philipp Deppenwiese
Changes since SeaBIOS 1.9.3 Release 1.10.0: * Initial support for Trusted Platform Module (TPM) version 2.0 * Several USB XHCI timing fixes on real hardware * Support for "LSI MPT Fusion" scsi controllers on QEMU * Support for virtio devices mapped above 4GB * Several bug fixes and code cleanups Release 1.10.1: * Updates for QEMU for reproducible builds Change-Id: I465700307d72fa44b6900b38b332603ea505ed09 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18026 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-06arch/x86: fix cmos post logging in non romcc bootblockAaron Durbin
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18043 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-05src/amd: Add common definition of AMD ACPI MMIO addressTimothy Pearson
The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-05mb/ga-m57sli-s4: Fix early uart outputArthur Heymans
The console output is garbled until it is fixed in ramstage by devicetree which sets the uart clock predivider correctly. Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17969 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-04util/crossgcc: update jenkins-build-toolchainMartin Roth
This allows the make jenkins-build-toolchain to use the BUILDGCC_OPTIONS variable. Previously, the options were hardcoded. Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17766 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-04buildgcc: Remove quotes around a $CC callNico Huber
If we use ccache we have to interpret spaces in $CC as separation characters. The downside is that we can't support spaces in the compiler's path. But, well... Change-Id: I4e6e6324389354669a755f570083a40ff00b1bbf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18018 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-01-04util/cbfstool: Fix to build with latest llvmManoj Gupta
cbfs-payload-linux.c:255:43: note: add parentheses around left hand side expression to silence this warning if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { [pg: also fix the semantics. Thanks Nico for catching this] BUG=chromium:665657 TEST=coreboot-utils builds Change-Id: I025c784330885cce8ae43c44f9d938394af30ed5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35c4935f2a89c3d3b45213372bcf0474a60eda43 Original-Change-Id: I8758e7d158ca32e87107797f2a33b9d9a0e4676f Original-Reviewed-on: https://chromium-review.googlesource.com/411335 Original-Commit-Ready: Manoj Gupta <manojgupta@chromium.org> Original-Tested-by: Manoj Gupta <manojgupta@chromium.org> Original-Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://review.coreboot.org/17568 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-04google/auron: Fix omitted ACPI KB backlight for variantsMatt DeVillier
Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-04vboot: Remove rmu.bin from FW_MAIN_A and FW_MAIN_BLee Leahy
Add rmu.bin to the list of files that exist only in the read-only section (COREBOOT) of the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18031 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-01-04intel/i945 boards: Add romstage time stampsPaul Menzel
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-04soc/intel/quark: Add monotonic timer supportLee Leahy
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18002 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/romcc: remove dead assignmentsPatrick Georgi
Change-Id: Iab6fe065faeacfca3b41eb5bae1075dcfb1a2b05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: scan-build (clang 3.8) Reviewed-on: https://review.coreboot.org/18021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/romcc: Ensure that bit shift is validPatrick Georgi
Change-Id: Idbe147c1217f793b0360a752383203c658b0bdce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287090 Reviewed-on: https://review.coreboot.org/18020 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/romcc: avoid leaking a typePatrick Georgi
Only allocate ptr_type when it's actually used. Change-Id: Iea5f93601a42f02a1866bdff099f63935fdd5b8d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1129117 Reviewed-on: https://review.coreboot.org/18017 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/romcc: avoid dereferencing NULL pointerPatrick Georgi
argv is only filled for macro->argc > 0. Change-Id: I5ff21098384afc823efa14be3d5565507fb2b3b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287089 Reviewed-on: https://review.coreboot.org/18016 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/romcc: free variable after usePatrick Georgi
closure_type is copied then never used again. Close that leak. Change-Id: Idd4201f7fc6495fde5ad2e1feb7e499e38986e92 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287073 Reviewed-on: https://review.coreboot.org/18015 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03broadcom/bcm5785: don't treat KBC-DATA as COM1Patrick Georgi
Add a break statement instead. While there, fix a bunch of typos in comments. Change-Id: I465c0188d4b46eabf8d17e69fa0fdc6a9c2ad66e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229645 Reviewed-on: https://review.coreboot.org/18013 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV.Hung-Te Lin
When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try to load VBNV from flash if the VBNV in CMOS is invalid. This is usually correct, except the case of battery cut-off. CMOS will always be invalid after battery cut-off if there is no RTC battery (or if that is dead). However, in current implementation the backup in flash is only updated in coreboot, while the real battery cutoff (and the clearing of cutoff flags in VBNV) is done in payload (Depthcharge) stage. This will create an endless reboot loop that: 1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot. 2. coreboot backs-up VBNV_CMOS to VBNV_flash. 3. Depthcharge sees cutoff flag in VBNV_CMOS. 4. Depthcharge clears cutoff flag in VBNV_CMOS. 5. Depthcharge performs battery cutoff (CMOS data is lost). 6. (Plug AC adapter) Reboot. 7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash. 8. Jump to 3. As a result, we should always clear battery cutoff flags when loading backups from VBNV_flash. BRANCH=glados,reef BUG=chrome-os-partner:61365,chrome-os-partner:59615 TEST=emerge-reef coreboot bootimage; Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/423460 Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/18008 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03rockchip/common: Loosen I2C frequency target requirementsJulius Werner
I've recently added an assertion to ensure that the effective I2C frequency on Rockchip SoCs is not too far off the 400KHz target due to divisor rounding errors. A 10KHz margin worked fine for RK3399, but it turns out that RK3288 actually only ever hit 387KHz since its I2C clocks are based off the already pretty low 75MHz PCLKs. While we could probably change the PCLKs to make this closer, that seems like a too intrusive change for something that has already worked just fine for years, so just loosen the restriction a little more instead. BRANCH=None BUG=chromium:675043 TEST=None Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421095 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/18007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03i2c/tpm: Ignore 0xFF bytes for status and burstCountJulius Werner
We've found that the SLB9645 TPM sometimes seems to randomly start returning 0xFF bytes for all requests. The exact cause is yet unknown, but we should try to write our TIS code such that it avoids bad interactions with this kind of response (e.g. any wait_for_status() immediately succeeds because all "status bits" are set in the response). At least for status and burstCount readings we can say for sure that the value is nonsensical and we're already reading those in a loop until we get valid results anyway, so let's add code to explicitly discount 0xFF bytes. BRANCH=oak BUG=chrome-os-partner:55764 TEST=None Change-Id: I934d42c36d6847a22a185795cea49d282fa113d9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420470 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/18006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03Revert "google/oak: increase the driving strength for 4GB DRAMs"Nicolas Boichat
This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which appears to cause random stability issues on some elm units. BRANCH=oak BUG=chrome-os-partner:60869 BUG=chromium:673349 TEST=None Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567 Reviewed-on: https://chromium-review.googlesource.com/419862 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18005 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Add early debugging codeLee Leahy
Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Fix serial port configurationLee Leahy
Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/abuild: Don't set XGCCPATH if it's in the environmentMartin Roth
Change-Id: I0fa231ca3d33300a671810e994c5be54ac10a18b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-03mb/asus/p5gc-mx: Remove extra BSEL strap checkArthur Heymans
This extra check is based on comparing CPU BSEL pins and reports in MCH configuration. This gives false positives in the case of 1333MHz CPUs which automatically get downgraded to 1067MHz by the northbridge (max supported frequency by 945gc). TESTED with Intel Xeon 5460 (does not boot but completes raminit) Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03mb/intel/d945gclf: Fix resume from S3 suspendArthur Heymans
Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives. Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03util/inteltool: Add ICH6-10 to BIOS_CNTL listArthur Heymans
Without this change inteltool cannot read BIOS_CNTL values nor can it read the SPIBAR values. Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17979 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03util/inteltool: Fix ICH SPIBAR registersArthur Heymans
The ICH7 SPIBAR offset and registers are different from later generation. ICH8 has a different offset from later generation. ICH6 has no SPI controller. Change-Id: I7691bce619089b15805114047bcb1fd121a5722b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03sb/nvidia/mcp55: Fix P_state generationArthur Heymans
amd_generate_powernow is never called by in lpc_slave_ops. Move it to lpc_ops like on all other AMD southbridges. TESTED on Gigabyte ga-m57sli-s4 Change-Id: I7db036e681d591a19e15dd3eaafb88b72a41bea1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03mb/ga-m57sli: Add cmos.defaultArthur Heymans
If the cmos checksum is incorrect it should fall back to sane defaults. Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17968 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03superiotool: Add support for HWM registers on W83627EHGArthur Heymans
Based on datasheet: "W83627EHF/EF W83627EHG/EG WINBOND LPC I/O, Revision : 1.0" Change-Id: Ia2e5ab8bc454a34a89fe2cf06bfba55261109785 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17457 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03superiotool: Add support for HWM registers on W83627DHGArthur Heymans
Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4" Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17964 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03mainboard/google/reef: Update DPTF parameters EVT1_v0.3Tim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17975 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03sb/intel/common/gpio: Support ICH9M and priorPatrick Rudolph
Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18012 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-01-02util/cbfstool: Don't print region information on stderr by defaultPatrick Georgi
It's usually not too interesting, so hide it behind -v. Change-Id: Icffb5ea4d70300ab06dfa0c9134d265433260368 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/17899 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-30drivers/uart/oxpcie_early.c: remove uart_fill_lb()Martin Roth
uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the Oxford OXPCIe952 Kconfig option is enabled, we were getting an error. "multiple definition of `uart_fill_lb'" The new version of uart_fill_lb sets the regwidth depending on the Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't give DRIVERS_UART_OXPCIE as a choice. Change-Id: Ife24ab390553b10b2266809595c2e06463de708c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-29Kconfig: Document what ASPM meansJonathan Neuschäfer
Change-Id: I57dd933ad70ffac95388d832bd5047f2225688e3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17973 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-29payloads/external: Download FILO over HTTPSJonathan Neuschäfer
Change-Id: I1b44e32505b96978849d39764ff399a502fa6e84 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17972 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-29payloads/external: Download iPXE over HTTPSJonathan Neuschäfer
Change-Id: Ie4979ab8491ee821b39a273c5f354c445105d2a4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-28mb/asus/p5gc-mx: Fix and complete SIO devicetree optionsArthur Heymans
The devicetree lacks the 'chip' option for the Super I/O, which causes the Super I/O related entries to be ignored. This also adds other LDN that are present on this Super I/O. Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17965 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-28util/intelmetool: Fix warning building with 32-bitPaul Menzel
On a 32-bit system, pointers are 32-bit wide, and not 64-bit, resulting in the warning below. ``` mmap.c: In function ‘map_physical_exact’: mmap.c:26:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] virt_addr = mmap((void*)mapto, len, PROT_WRITE | PROT_READ, ^ ``` Fix this by using compatible types. Change-Id: I4ede26127efcbd5668b978e6880a0535607e373d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17970 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-28buildgcc: Indicate CXXFLAGS for binutilsNico Huber
CXXFLAGS seems to be used a lot and have to be specified independently from CFLAGS. Change-Id: Iff4c76e54a46e908299b532fd848165a3dc04d43 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17937 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-28buildgcc: Fix string comparison operatorNico Huber
Change-Id: I8ff8d51507dcf12cd554c8b4713074a99e47c11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17942 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-28Microcode: Show a useful warning when microcode bins are missingMartin Roth
Because the binary repo is disabled by default, we get frequent questions about why the build failed, relating to microcode in the binary repository. - Show an error saying that the file is missing instead of the typical make error of no rule to build the file. - Show a note encouraging users to try enabling the binary repo if it's not enabled. Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-27buildgcc: Build GMP `--with-pic` if GCC defaults to `-pie`Nico Huber
GCC 6 can optionally default to building all binaries as position independent executables (PIE). This breaks linking against static libraries that are compiled without position independent code (PIC). Building GMP `--with-pic` in this case seems to be the least fragile solution. TEST=Run `make all` and `make BUILDGCC_OPTIONS=-b build-i386` in util/crossgcc on Debian Stretch. Change-Id: I5f3185af9c8d599379a628e18724b217b88be974 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17936 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-12-27device/dram/ddr3: add FTB timingsNicola Corna
SPD revision 1.1 introduced FTB timings, an extra set of SPD values that specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin. For backwards compatibility, the MTB is usually rounded up and the FTB part is negative. For this reason some memories were not set up optimally, as the FTB part was ignored and the resulting timing wasn't set to the minimum value. The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E (1866 MHz): reading only the MTB part, coreboot reports a tCKmin of 1.125 ns, corresponding to a working frequency of 800 MHz; with the additional tCKmin FTB part (-0.054 ns) the new (rounded) value is 1.070 ns, valid for a 933 MHz operation. Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is now detected as DDR3-1866 instead of DDR3-1600. Some manufacturers (like Micron) seems to expect a small rounding on the timings, so a nearest-value rounding is performed. If this assumption isn't correct, an error up to ~2 ps can be committed, which is low enough to be safely ignored. Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/17476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-27console: Enable do_printk_va_list for VBOOTLee Leahy
Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals in include/console/console.h and the only caller is vboot/vboot_logic.c. CONFIG_VBOOT is also selected for CONFIG_CHROMEOS. TEST=Build and run on Galileo Gen2 Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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