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2020-09-03mb/google/zork: update DRAM table for berknipKevin Chiu
Add Dual DDR4 Samsung K4AAG165WA-BCTD 16Gb x 8 BUG=b:165956925 BRANCH=zork TEST=1. gen part id by gen_part_id 2. emerge-zork coreboot Change-Id: Ia21a561e9b89feeccb6509d9280eaf52cfc2f5a3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-03trogdor: Assert EN_PP3300_HUBJulius Werner
Some Trogdor variants power their USB hub from a PMIC LDO that is already enabled by QcLib, and some have a discrete LDO that is controlled by GPIO_84. For the latter, let's make sure we assert that GPIO on boot. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9d206cd7154ded3bf179e68c2b1421d0a8ee89f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: mturney mturney <mturney@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-03trogdor: Shuffle RAM and SKU ID pins (again)Julius Werner
We're moving a lot of pins around on Trogdor again. For firmware this only affects the RAM and SKU strapping ID pins. Since there are quite a few of the old devices in circulation this time and some people seem to care about mosys RAM information working, let's actually check the board revision and support both cases this time. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7728d8ea4b7f6e7ff6721ade90f975f6efd5ddd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-02mb/google/puff/var/noibat: Update DPTF parameters for noibatWisley Chen
1. Update paramerters form thermal team. 2. Update PL2 Max/Min to 51W/15W. BUG=b:167494420 BRANCH=puff TEST=build noibat and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/puff: Update DPTF parameters and TCC offset for faffyDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-02mb/*/Kconfig: Drop redundant 'select DRIVERS_INTEL_WIFI'Elyes HAOUAS
DRIVERS_INTEL_WIFI is already set to yes. Change-Id: I09f628a9c1feb8992b6fe7c7ca93c75243ffc0f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02Revert "mb/google/volteer/variant/lindar: Update memory settings."Patrick Georgi
This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb. Reason for revert: broke the build Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44993 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02mb/google/volteer/variant/lindar: Update memory settings.rasheed.hsueh
Based on the Lindar's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-02mb/google/poppy/var/rammus: Update SPD table for RammusKane Chen
1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex". 2. Add SPD support in Rammus memory table, as follows: SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 BUG=b:166576463 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util: update .gitignore to ignore spd_tools binariesRob Barnes
Ignore spd_tools binaries. BUG=None TEST=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ib5759157b668085866d0164301d84e3c15a9ef00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44951 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guideSubrata Banik
BUG=b:153888802 TEST=Able to list correct eSPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read eSPI/EC Bus Frequency: 60MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guideSubrata Banik
BUG=b:153888802 TEST=Able to list correct SPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCHSubrata Banik
BUG=b:153888802 TEST=Able to dump FLMAP3 for Volteer platform with TGP > ifdtool -d coreboot.rom FLMAP3: 0x00000000 Minor Revision ID: 0x0000 Major Revision ID: 0x0000 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCHSubrata Banik
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH BUG=b:153888802 TEST=Dump FD for Hatch platform as below > ifdtool -d coreboot.rom PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02util/ifdtool: Identify between ICH and PCH RevisionSubrata Banik
Consider IBEX_PEAK onwards all chipsets are belong to PCH family. BUG=b:153888802 TEST=Able to print correct PCH revision on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point With this CL : PCH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02mb/google/sarien/Kconfig: Drop redundant 'select TPM2'Elyes HAOUAS
TPM2 set to yes by MAINBOARD_HAS_TPM2 at security/tpm/Kconfig file. Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES'Elyes HAOUAS
GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-02mb/google/kukui: Add LPDDR4X support for fennel/cerise/sternxuxinxiong
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10 BUG=b:162891673 BRANCH=kukui TEST=make Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-09-01mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL'Elyes HAOUAS
'CONSOLE_SERIAL' is already set to 'y' at src/console/Kconfig. Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-01mb/google/puff: Update DPTF parameters for kaisa and duffyDavid Wu
1. Apply the DPTF parameters receive from the thermal team. 2. Change PL2 min value from 25W to 15W. 3. Change PL2 max value from 64W to 51W. BUG=b:166696500 BRANCH=puff TEST=build and verify by thermal team Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-01mb/google/puff: Convert ASL file to new DPTF dt implEdward O'Callaghan
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check. Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31mb/google/zork: Fix SPD typo in trembyle makefileRob Barnes
Relative path to spd directory was wrong. BUG=b:167175547 TEST=Boot Trembyle SKU 2 Change-Id: I63ae4f39ba69d2d80c25ac7383b6eb953901f56d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44946 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31Documentation: Discuss how we use languagePatrick Georgi
Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31device: Add method to configure bus mastering based on KconfigFelix Singer
The bus master bit is set at many places in coreboot's code, but the reason for that is not quite clear. We examined not setting the bus master bit whereever possible and tried booting without it, which worked fine for internal PCI devices but not for PCIe. As a PCIe device we used a Samsung M.2 NVMe SSD. For security reasons, we would like to disable bus mastering where possible. Depending on the device, bus mastering might get enabled by the operating system (e.g. for iGPU) and it might be required for some devices to work properly. However, the idea is to leave it disabled and configure the IOMMU first before enabling it. To have some sort of "backwards compatibility", add a method which configures bus mastering based on an additional config option. Since CB:42460 makes usage of this treewide, enable it by default to keep the current behaviour for now. Tested with Siemens/Chili, a Coffee Lake based platform. Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: Fix active polarity of REPORT_EN pin in overridetreeFurquan Shaikh
GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means enable operation and 0 means stop operation. Override tree exposes this pin as stop GPIO. Thus, it needs to be configured as active low i.e. 0 = active (stop), 1 = inactive (enable report). Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31mb/google/zork: Fix active polarity of touchscreen reset GPIO in overridetreeFurquan Shaikh
v3.6+ of reference schematics have moved to using active low polarity for touchscreen GPIO. This change sets the default polarity in override tree accordingly to active low. To support boards from older builds, variant_touchscreen_update() already updates the polarity to active high. BUG=b:161937506 Change-Id: I370bdb27ea5d0601612d13b515113a6048018964 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31Documentation: Update release notes for x86_64Patrick Rudolph
Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
Clone entirely from Jasperlake This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/36550 List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 6. Add required headers into include/soc/ from JSL directory Elkhart Lake specific changes will follow in subsequent patches. 1. soc/intel/elkhartlake: Update Kconfig Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-31util/ifdtool: Identify chipset without platform nameSubrata Banik
Able to uniquely identify the chipset without specifying the platform specific quirks (adl/cnl/icl/jsl/tgl etc.). BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 100 series Sunrise Point With this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I83763adb721e069343b19a10e503975ffa6abb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31util/ifdtool: Skip unused and reserved Flash RegionSubrata Banik
This patch ensures all unused and reserved flash region sections are not getting listed while using -d option to dump FD. BUG=b:153888802 TEST=List only used flash region section with below command > ifdtool -p tgl -d coreboot.rom Without this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG5: 0x00007fff Flash Region 5 (Reserved): 07fff000 - 00000fff (unused) FLREG6: 0x00007fff Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) FLREG7: 0x00007fff Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) With this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31util/ifdtool: Add platform specific quirks for ADL/ICL/JSL/TGLSubrata Banik
BUG=b:153888802 TEST=Able to dump FD contain using below command > ifdtool -p tgl -d coreboot.rom Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31arch/x86/exit_car.S: Fix checking clflush supportArthur Heymans
The BT instruction stores its result in CF and not ZF so use the correct jump instruction. This fixes a hang in postcar on CPUs lacking support for this instruction. This concerns older pre-SSE2 hardware. Change-Id: I704e3c579150fb9b9a292ef0e83050e7bf7cb078 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-31mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVPShreesh Chhabbi
These changes are according to spd_binary_optimization_volteer_v0.4 sheet. Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/dedede/var/drawcia: Add elan USI touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-31Makefile.inc: Print warning type ignored by IASLMaxim Polyakov
- Use a new variable to store the list of warning types; - print this list when building an image. TEST = build image on Kontron mAL-10 COMe module: IASL 3150 2158 3133 warning types were ignored! IASL build/dsdt.aml disassembled correctly. Change-Id: I46f761612254b400563f8567be9bd61601f23467 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31mb/amd/mandolin: move PCIe GPP clock setting to devicetreeFelix Held
Checked with the schematics that all PCIe clocks have a corresponding clock enable pin. BUG=b:149970243 BRANCH=zork Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork/dalboz: move PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork/trembyle: add PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
The _SHIFT postfix is a bit clearer than the _SHL one and more in line with the names used for this kind of defines in coreboot. The documentation on that register is currently wrong and will hopefully be fixed in the future; the defines should now match the hardware. BUG=b:149970243 BRANCH=zork Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31include/device/azalia_device: Fix typoPatrick Rudolph
The code using the macro was found not working after finally enabling the HDA PCI device on the hermes board. Fix a typo to generate the correct verbs. Tested on prodrive/hermes. Change-Id: I953c2e9fbebc1f02bdf71ce868a95f578300c3a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31gitignore: Remove obsolete pathsElyes HAOUAS
Change-Id: I3288fd3cd6df44cdaddff0b225d4dc9eb8300378 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44898 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31lint/lint-extended-007-checkpatch: Remove obsolete pathElyes HAOUAS
Change-Id: I8a91d2a8bc6a1fa709aeadd3b7482d1785068276 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31mb/google/zork: update GPIO config for dirinbozKevin Chiu
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 17:52:42 +0000