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2019-01-24Kconfig: Remove symbol names for choicesNico Huber
These are completely throwing Kconfig off, resulting in duplicate entries. Change-Id: I401467da686d5011a456b661a10170492a919c81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24cpu/intel/model_406dx: Remove the notion of CPU socketsArthur Heymans
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31032 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: More SMBus block_cmd_loop()Kyösti Mälkki
Setup to different block transactions are similar enough to have common place to call execute_command() in. Change-Id: I671fed280f47e6bc673eb7506f09ed6ed36d2804 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus block_cmd_loop()Kyösti Mälkki
For debugging prints, report the number of loop spent polling instead. Change-Id: I61865aaafc9f41acd85c5dc98817d12642965ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21121 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus complete_command()Kyösti Mälkki
Adds helper to test for SMBHSTSTAT flags for hardware having finished or failed a transaction. Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus execute_command()Kyösti Mälkki
Implement the common start of transaction. Fixes a problem where smbus_wait_until_active() can miss SMBHSTSTS_HOST_BUSY being set, if transaction completes very fast. Or if we are single-stepping or executing under SerialIce emulation. Change-Id: Icb27d7d6a1c54968950ca292dbae05415f97e461 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus setup_command()Kyösti Mälkki
Implements the common parts of any SMBus transaction with a stub to log and recover (TBD) from timeout errors. Bits in SMBHSTCTL register are no longer preserved between transactions. Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24mb/ocp/wedge100s: Add SuperIO supportPatrick Rudolph
* Enable COM1, COM2, PMC1 and PMC2 TODO: Look at additional configuration and EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24superio/ite: Add it8528ePatrick Rudolph
* Add support for the SuperIO part of IT8528E * Based on the IT8528E datasheet and tests on vendor firmware TODO: Add support for accessing EC space, which should be implemented in src/ec/ instead, as it's a separate logical unit. No datasheet is publicy available. Tested on wedge100s. The serial works under the OS without CONFIG_CONSOLE_SERIAL. Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24AGESA fam12/fam14: Drop amdfamX.c file includeKyösti Mälkki
Quick and ugly approach, just paste the file in place, dropping any __PRE_RAM__ parts. That's the way it was previously done for fam15tn already, refactoring common parts will happen on a later date. Change-Id: I29fd421fb4aef984d117912ac836dee71d3d73ea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24superio/it8716f: fix pnp_dev_infoFelix Held
Change-Id: If6a4b6f52425a795af34264ab839968b36a117eb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/30960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24superio/wpcm450: fix keyboard IO masksFelix Held
The two IO regions of the keyboard controller are 1 byte long, not 8. Change-Id: I7319ce9f84181759f4dc7b59c0020f3a5dd5dc03 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/30958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-23mb/google/sarien: Replace B0D4 with TCPUSumeet Pawnikar
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
Replace device name from B0D4 with TCPU for DPTF sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23mb/*/*/devicetree.cb: Make sandybridge devicetree uniformArthur Heymans
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-23i945,ICH7: Write on RPFN only onceElyes HAOUAS
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write. Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-23soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeoutDaniel Kurtz
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-23mb/intel/icelake_rvp: Enable dptf functionalitySumeet Pawnikar
Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/29686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23mb/intel/glkrvp: Fix termination for dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23util/lint: Update non-ascii linter for FreeBSDMartin Roth
On FreeBSD, this test was failing with the error: "grep: Argument list too long" - Remove support for testing coreboot not in a git repo. Many of the other linters already don't support this. - Use git grep to find offending files, then xargs to print out the lines. Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-23google/kukui: Revise FMAP layout for larger CBFSHung-Te Lin
Kukui with vboot enabled will build with `detachable_ui`, which needs larger space in CBFS for more complicated assets. So we need to revise FMAP sections: - BOOTBLOCK (not really used) only needs <= 32K. - GBB can be much smaller since assets moved from GBB to CBFS. - FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can get larger continuous space. - COREBOOT(CBFS) should take all space left. Since FMAP and COREBOOT have changed location, the system will need to reflash EC (which contains the new bootblock) as well. BUG=b:123202015 TEST=Builds and boots on Kukui P1 Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23mb/google/poppy/variant/nami: disable unused usb2 portsRen Kuo
disable unused usb2 ports of bard and ekko skus BUG=120874946 TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30986 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/arcada: Add settings for noise mitgationCasper Chang
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-23mb/lenovo/x131e: add VBTJames Ye
VBT was extracted from VBIOS ROM. Tested with libgfxinit, booting SeaBIOS into Linux. Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/pineview: Use parallel MP initArthur Heymans
Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
Use parallel MP init code to initialize all AP's. Also remove guards around CPU code where all platforms now use parallel MP init. This also removes the code required on lapic init path for model_6fx, model_1017x and model_f4x as all platforms now use the parallel MP code. Tested on Intel DG41WV, shaves off about 90ms on a quad core. Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/i945: Use parallel MP initArthur Heymans
Use the parallel mp init path to initialize AP's. This should result in a moderate speedup. Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is 26ms faster compared to lapic_cpu_init. This removes the option to disable HT siblings. Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-23nb/intel/gm45: Use parallel MP initArthur Heymans
This places the parallel mp ops up in the model_1067x dir and is included from other Intel core2 CPU dirs that can use the same code. Tested on Thinkpad X200 on which boot time is reduced by ~35ms. Change-Id: Iac416f671407246ee223075eee1aff511e612889 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/23434 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mediatek/mt8183: Add Micron 4GB LPDDR4X DDR supportHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-23soc/intel/baytrail/romstage: Remove unneeded white spaceElyes HAOUAS
Change-Id: I6725d1130a40d3c458a3cd5a116d6e91354ec41b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23src/drivers: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-01-23mb/purism/librem_skl: add 13v3 variantMatt DeVillier
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged since boards were initially shipped with 13v2 firmware, and changing it now would cause flashrom to throw a board mismatch error. Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: add support for 13v4/15v4 boardsMatt DeVillier
Add support for Kabylake Librem 13v4/15v4 boards, reusing existing 13v2/15v3 variants since board design unchanged (only SoC). Adjust identification strings, add Kabylake VGA PCI ID. Change-Id: Ia795b9c7373ea2e2acd3bef309320b58e9e8449d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: adjust CBFS_SIZEMatt DeVillier
Adjust default CBFS_SIZE to match that used in configs for building Change-Id: Ibe1312560a923dcdefb8af52a721ab76c0b08a2e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/google/poppy/variants/nami: close the FP power in S5Ren Kuo
close the FP module power in power off (s5) BUG=122887366 BRANCH=Nami TEST= build test firmware and measure the fp power enable pin Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30910 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Vincent Wang <vwang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/hatch: Enable SD card support for hatchMaulik V Vaghela
Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=Verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-23arch/x86: Align _start16bit with C_ENVIRONMENT_BOOBLOCKKyösti Mälkki
Followup removes SIPI_VECTOR_IN_ROM and it seems reasonable enough to force the alignment unconditionally to page size. Reason for the conditionals is the alignment is not possible with romcc bootblocks having total size less than 4 kiB. Change-Id: I0ff2786f80a319ebb3215d4fd696cda3e15c3012 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23Drop leftover debug function declarationsKyösti Mälkki
Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Add BMC KCS to ACPITimothy Pearson
The BMC KCS interface must be advertised to the host OS in order for automatic load of the ipmi module to work. Expose the KCS interface via ACPI. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19822 Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Enable IPMI KCS accessTimothy Pearson
The on-board BMC contains a hardware KCS interface. Allow access to it over LPC. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac6 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22util/crossgcc: use fixed length version string.Wonkyu Kim
After merging util/crossgcc: derive date and version from latest commit (https://review.coreboot.org/c/coreboot/+/30804), crossgcc build is broken in internal repository due to long version name;coreboot.org repository is ok because it uses short tag name. The patch uses "git describe" which is dependent on git tag name. If tag name is little bit long, it can cause crossgcc build failed. To avoid this issue, use only short version of hash string which is fixed length. And it's enough as version string, because we also use date(CROSSGCC_DATE) together. TEST=Build crossgcc in both coreboot.org and internal repository which uses longer tag name and check version string in build log. Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/31001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-22Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"Daniel Kurtz
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22AGESA/binaryPI: Add NULL pointers checkKyösti Mälkki
Fix regression after commits 4ad7f5b AGESA: Use pcidev_on_root() 33ff44c binaryPI: Use pcidev_on_root() Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes would be ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-22cpu/intel/model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR'sArthur Heymans
Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for that before enabling this feature. This also exposes a function to fetch whether alternative SMRR MSR's ought to be used. Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selectionSubrata Banik
hatch shouldn't make use of internal ec.bin through IFD tool. Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-21Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"Raul Rangel
This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26. Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit. e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch. We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs. Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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