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2016-07-08google/reef: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08siemens/mc_bdx1: Move SCI to IRQ 10Werner Zeh
IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15563 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07mainboard/google/reef: apply EVT board changesAaron Durbin
Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15562 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add board_id() supportAaron Durbin
The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15561 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add memory SKU id supportAaron Durbin
While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15560 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc/intel/apollolake: add LPDDR4 sku selection supportAaron Durbin
Instead of having all the mainboards put similar logic into their own code provide common mechanism for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15559 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc/intel/apollolake: make internal pulls weak for gpio inputsAaron Durbin
The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07lib/gpio: add pullup & pulldown gpio_base2_value() variantsAaron Durbin
Provide common implementations for gpio_base2_value() variants which configure the gpio for internal pullups and pulldowns. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I9be8813328e99d28eb4145501450caab25d51f37 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15557 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
Have acpigen_write_package() return a pointer to the package element counter so it can be used for dynamic package generation where needed. Change-Id: Id7f6dd03511069211ba3ee3eb29a6ca1742de847 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07soc: Remove newline from `CHIP_NAME`Paul Menzel
The name must not terminated with a newline character `\n` as it would make it hard to use it strings. So, remove the newline from the two SoCs with it. Change-Id: I7570442b38a455e7c497d7f461c208fb0a88296d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15540 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07lenovo/t530: Don't enforce native gfx initAlexander Couzens
Change-Id: I6d51f46240c62fcd6089411e8681e0b6e7d5bfe4 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/15222 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-07lenovo/t530: add VGA device ID 8086,0106Alexander Couzens
Change-Id: I3cffe9d832edbbea79cabca639d9d920b7ffcf9a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/8178 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-07nyan: Avoid running early_mainboard_init twice in vboot contextPaul Kocialkowski
A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-07tegra124: Build verstage when CHROMEOS is selectedPaul Kocialkowski
This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15451 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/15346 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-07-07MAINTAINERS: Add myself as tpm support maintainer.Philipp Deppenwiese
The tpm software stack, drivers and trustedboot needs to be maintained. Change-Id: I7b9ff9c4d7504c861de98ef3d8fcda53b20657c4 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/15312 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
2016-07-07board/intel/amenia: Enable LPSS S0ixHannah Williams
This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-07siemens/mc_bdx1: Set up opcode menu for SPI controllerWerner Zeh
Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-07intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPIWerner Zeh
The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2016-07-06siemens/mc_bdx1: Add usage of Siemens NC FPGA driverWerner Zeh
Enable NC FPGA driver for this mainboard. Change-Id: I87b6b10038f3d161a25b2008b7ea44b5627cca43 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15545 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-06siemens/nc_fpga: Add driver for Siemens NC FPGAWerner Zeh
Add driver code to initialize Siemens NC FPGA as PCI device. Beside some glue logic it contains a FAN controller and temperature monitor. Change-Id: I2cb722a60081028ee5a8251f51125f12ed38d824 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-06PCI: Use PCI_DEVFN macro instead of DEV_FUNCWerner Zeh
There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-05buildgcc: Add option to bootstrap a host gccNico Huber
Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) o FreeBSD 10.3 (x86_64) (with gcc-aux package) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) v5: Rebased after toolchain updates to GCC 5.3.0 etc. Build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Debian 8 "Jessie" (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-05buildgcc: Make package build() function more versatileNico Huber
Refactor build() to make things more flexible: Add a parameter that tells if we build a package for the host or for a target architecture. This is just passed to the build_$package() function and can be used later to take different steps in each case (e.g. for bootstrapping a host gcc). Move .success files into the destination directory. That way we can tell that a package has been built even if the package build directory has been removed. Change-Id: I52a7245714a040d11f6e1ac8bdbff8057bb7f0a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-05siemens/mc_bdx1: Set up MAC address for available i210 MACsWerner Zeh
Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-04fmaptool: Accept hex values with uppercase lettersPatrick Georgi
Due to a newer flex version with which the scanner was recreated, we also have to make the compiler less strict on the generated code. Change-Id: I3758c0dcb2f5661d072b54a30d6a4ebe094854e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/15482 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02soc/apollolake: Allow enable/disable of LPSS S0ix from devicetreeSaurabh Satija
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Add GPE routing codeShaunak Saha
This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02cbfstool: Require "-m ARCH" to extract payloads and stagesAntonello Dettori
Require the user to specify which architecture the payload/stage was built for before extracting it. Change-Id: I8ffe90a6af24e76739fd25456383a566edb0da7e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not neededAndrey Petrov
On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15494 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02google/reef: Add DA7219 support in acpiSathyanarayana Nujella
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add Audio DSP deviceHarsha Priya
Add the Audio DSP device for apollolake as a PCI driver with a static scan_bus handler so generic devices can be declared under it. This is for devices like the Maxim 98357A which is connected on the I2S bus for data but has no control channel bus and instead just has a GPIO for channel selection and power down control and needs to describe that GPIO connection to the OS via ACPI. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/15528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02cbgfx: Use memset() for faster screen clearing if possibleJulius Werner
cbgfx currently makes a separate function call (recomputing some values) for every single pixel it draws. While we mostly don't care that much about display speed, this can become an issue if you're trying to paint the whole screen white on a lowly-clocked Cortex-A53. As a simple solution for these extreme cases, we can build a fast path into clear_screen() that just memset()s the whole framebuffer if the color and pixel format allow it. BUG=chrome-os-partner:54416 TEST=Screen drawing speed on Kevin visibly improves (from 2.5s to 3ms). Change-Id: I22f032afbb86b96fa5a0cbbdce8526a905c67b58 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15524 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: handle p2sb quirksAaron Durbin
The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-02amd/olivehillplus: Fix PCIe lane number comments.Derek Waldner
Correct the GPP PCIe lane number comments so that they match the code. Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25 Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com> Reviewed-on: https://review.coreboot.org/15095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
Have the different acpi_device_ path functions use a different static buffer so they can be called interchangeably. Change-Id: I270a80f66880861d5847bd586a16a73f8f1e2511 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02soc/intel/skylake: Add function for gpio_t to ACPI pin translationDuncan Laurie
Add the function defined in gpio.h to translate a gpio_t into a value for use in an ACPI GPIO pin table. For skylake this just returns the gpio_t value as the pins are translated directly and they are all in the same ACPI device. Change-Id: I00fad1cafec2f2d63dce9f7779063be0532649c7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15520 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02drivers/generic/max98357a: Fix naming and ACPI path handlingDuncan Laurie
The upstream kernel driver is not using the of-style naming for sdmode-gpio so remove the maxim prefix, and remove the duplicate entry for the sdmode-delay value as well. Also fix the usage of the path variable, since the device path uses a static variable it can't be assigned that early or it will be overwritten by later calls. This results in the following output for the _DSD when tested on reef mainboard: Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x02) { Package (0x02) { "sdmode-gpio", Package (0x04) { \_SB.PCI0.HDAS.MAXM, Zero, Zero, Zero } }, Package (0x02) { "sdmode-delay", Zero } } }) Change-Id: Iab33182a5f64c89151966f5e79f4f7c30840c46f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15514 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate gpio_t into ACPI pinDuncan Laurie
There are four GPIO communities in this SOC and they are implemented as separate ACPI devices. This means the pin number that is used in an ACPI GPIO declaration needs to be relative to the community that the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig so this function actually gets used. This was tested on the reef mainboard by verifying the output of the SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed as pin 0x24 which is the value relative to the Northwest community. Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
Add a function for an SOC to define that will allow it to map the SOC-specific gpio_t value into an appropriate ACPI pin. The exact behavior depends on the GPIO implementation in the SOC, but it can be used to provide a pin number that is relative to the community or bank that a GPIO resides in. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659bcf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15512 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02google/reef: ACPI: Move touchpad to SSDT and remove TPMDuncan Laurie
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add support for LPSS I2C driverDuncan Laurie
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate device into ACPI nameDuncan Laurie
Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01lib: remove ulzma()Aaron Durbin
That function is no longer used. All users have been updated to use the ulzman() function which specifies lengths for the input and output buffers. Change-Id: Ie630172be914a88ace010ec3ff4ff97da414cb5e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15526 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-01Kconfig: Show DEBUG_BOOT_STATE in the Debug menuJonathan Neuschäfer
Change-Id: I22441ee0d19aa1b2e2f40278ce30092c86e0adc9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15522 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01AGESA boards: Fix split to romstage and ramstageKyösti Mälkki
Boards broken with commit: 062ef1c AGESA boards: Split dispatcher to romstage and ramstage Boot failure with asus/f2a85-m witnessed around MemMS3Save() call, message "Save memory S3 data in heap" in verbose agesa logs was replaced by a system reset. Default stubs for MemS3ResumeConstructNBBlock() returned TRUE without initializing the block contents. This would not work for case with multiple NB support built into same firmware. MemMCreateS3NbBlock() then returned with S3NBPtr!=NULL with uninitialized data and MemMContextSave() referenced those as invalid pointers. There is no reason to prevent booting in the case S3 resume data is not passed to ramstage, so remove the ASSERT(). It only affects builds with IDSOPT_IDS_ENABLED=TRUE anyways. Change-Id: I8fd1e308ceab2b6f4b4c90f0f712934c2918d92d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-07-01util/kconfig: Fix gconfig buildJonathan Neuschäfer
This linker error was the problem: build/util/kconfig/zconf.tab.o: In function `conf_read_simple': /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' build/util/kconfig/zconf.tab.o: In function `sym_calc_value': /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' collect2: error: ld returned 1 exit status /home/jn/dev/coreboot/util/kconfig/Makefile:339: recipe for target 'build/util/kconfig/gconf' failed make: *** [build/util/kconfig/gconf] Error 1 Change-Id: I4a667c7c15b35618fb9ad536f2be5044b8031ab4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15505 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-01skylake: Generate ACPI timing values for I2C devicesDuncan Laurie
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO linesAbhay Kumar
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15447 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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