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2017-01-18configs/builder: Add Sandy/Ivy Bridge Thinkpad configurationsPhilipp Deppenwiese
The coreboot builder makes use of the pre defined configuration files by executing abuild with -d option. These configuration files contain a basic configuration. Change-Id: I41470fe7aaa0fdae545ad9d702326a202d0d2312 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-18cbfstool: Don't use le32toh(), it's non-standardNico Huber
It's a BSD function, also, we missed to include `endian.h`. Just including `endian.h` doesn't fix the problem for everyone. Instead of digging deeper, just use our own endian-conversion from `commonlib`. Change-Id: Ia781b2258cafb0bcbe8408752a133cd28a888786 Reported-by: Werner Zeh <werner.zeh@siemens.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18157 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-17Revert "mainboard/google/snappy: Add PowerResource for ELAN touchscreen"Martin Roth
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource for ELAN touchscreen) Change was out of date and broke the build. Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-17SeaBIOS: Add Kconfig option to set verbosity levelStefan Tauner
Previously SeaBIOS's default was used (1). This patch defaults to coreboot's console level instead which is approximately the same verbosity as SeaBIOS and thus what a user would probably expect. Change-Id: If79e5f40c9380bb527f870eeb7d0cb43faf00beb Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/18051 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-17util/scripts: extend cross-repo-cherrypickPatrick Georgi
The script now automatically discovers the original branch (if known) and configures itself appropriately. Additionally, commit messages for changes coming _from_ upstream will be prefixed with "UPSTREAM: ". With the optional --cros argument, it also adds a BUG/BRANCH/TEST block at the right place in the commit message (right above the metadata) if one doesn't already exist. Change-Id: I81864ddca62fd99a9eb905d7075e5b53f58c4eb5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18135 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17mainboard/google/reef: Ignore SPI IOSTANDBYLijian Zhao
SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/18137 Tested-by: build bot (Jenkins) Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17mainboard/google/snappy: Add PowerResource for ELAN touchscreenWisley Chen
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17366 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17Combine Baytrail ChromeOS devices using variant schemeMatt DeVillier
Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17google/enguarde,ninja: Prep for variant mergeMatt DeVillier
Minor cleanup for enguarde and ninja devices: - enguarde: correct trackpad I2C slave address - enguarde: remove unused trackpad ACPI devices - ninja: remove unused PS2 keyboard ACPI device Change-Id: I1beb34059ba318e2d496a59e4b482f3462faf232 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
The new name and location make more sense: - The instruction used to call into machine mode isn't called "ecall" anymore; it's mcall now. - Having SBI_ in the name is slightly wrong, too: these numbers are not part of the Supervisor Binary Interface, they are just used to forward SBI calls (they could be renumbered arbitrarily without breaking an OS that's run under coreboot). Also remove mcall_dev_{req,resp} and the corresponding mcall numbers, which are no longer used. Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18146 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16riscv/spike: Remove obsolete DRAM_SIZE_MB settingJonathan Neuschäfer
Change-Id: I4077739ac2be09107d8c5a3e4ae7ebd0da3cb876 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16mainboard/google/poppy: SD card changesFurquan Shaikh
1. Disable WP 2. Pass SD card detect info in ACPI BUG=chrome-os-partner:60713 BRANCH=None TEST=Verified that OS is able to detect SD card and read/write to it. Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-16mainboard/google/poppy: Update DQS and DQ Byte mappings for poppyRizwan Qureshi
poppy schematics have undergone change after review, update DQS and DQ Byte mappings based on the new schematics. BUG=chrome-os-partner:61856 BRANCH=None TEST= Build and boot all the poppy proto SKUs to OS. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-16riscv: get SBI calls to workRonald G. Minnich
SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18097 Tested-by: build bot (Jenkins)
2017-01-14amd/mct: Add default values to highest_rank_count for DDR2Timothy Pearson
The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18078 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-14soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetreeKane Chen
This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/18060 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-14apollolake: Update UPD header files for FSP 1.3.0Brandon Breitenstein
These updated header files contain USB tuning parameters as well as some general cleanup of unused parameters in the UPD Headers. This patch along with the upcoming FSP 1.3.0 release will allow for USB tuning on apollolake platforms. CQ-DEPEND=CL:*315403 BUG=chrome-os-partner:61031 Change-Id: Id7cce1ea83057630d508523ada18c5425804535e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/18046 Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13aopen/dxplplusu: Switch to 2MiB flashKyösti Mälkki
Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13mainboard/google/poppy: Disable EC SW syncFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that EC SW sync is disabled Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable touchscreen in ACPIFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that touchscreen works on poppy. Change-Id: I0fd605048b91b126ca5b5f8c1c4d6d3f46f866a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18113 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Martin Roth <martinroth@google.com>
2017-01-13mainboard/google/poppy: Correct the index for SPD binariesFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Picks up correct SPD for index. Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18112 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable SD cardFurquan Shaikh
BUG=chrome-os-partner:60713 BRANCH=None TEST=sdcard is detected. Change-Id: I9ec0cabff0ed7973f5e7dd2c1eae346ae6a1aa99 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18111 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13fsp_baytrail: Enable graphic init per defaultWerner Zeh
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13sb/nvidia/mcp55: Fix typo in nic.cMartin Roth
The comparison value was obviously wrong here. One too many 'f' characters. Found-by: Coverity Scan #1229588 & 1229604 Change-Id: Iedd4f956d846f1c8661390b346c7397346def86b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18100 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13rockchip/rk3288: rtc-rk808: fix rtc time reading issueJeffy Chen
After we set the GET_TIME bit, the rtc time can't be read immediately. We should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading RTC time will return a old time. BUG=chrome-os-partner:61078 BRANCH=veyron TEST=Build and Boot Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/423272 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727 Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/427522 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13gru: Tuning USB 2.0 PHY0 and PHY1 host-portWilliam wu
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase compatibility") bypass ODT to set the max driver strength for the Type-C otg-port, it works well on otg-port when connected with USB2.0 devices. Unfortunately, because the Type-C otg-port and host-port are consisted in one USB2 PHY, so bypass ODT will have an effect on both host-port and otg-port. I have tested the host-port eye-diagram, the result shows that if we bypass ODT, the host- port eye-diagram height will become to high, more than 500mv, this may cause USB 2.0 high-speed enumeration failure. This patch bypass ODT for host-port separately, and then we can reduce the host-port driver strength without affecting the otg-port driver strength. BRANCH=gru BUG=chrome-os-partner:60727 TEST=Boot system, run 'lsusb' command and check if the usb camera and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are on usb 1.1 hub, the issue happens. If not, try to run camera app and then close camera app, repeat until find that the usb camera is on the usb 1.1 hub. Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491 Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/425739 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Inno Park <ih.yoo.park@samsung.com> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/18126 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13libpayload: usb: Reset ohci controller when trying to shutdown ohciJeffy Chen
Currently we just disabled ohci interrupts when calling ohci_shutdown, Which would not actually shutdown the ohci controller, for example it may still written the increased HccaFrameNumber to Hcca buffer. Perform a soft reset to ohci controller as the linux kernel ohci-hcd driver does. BUG=chrome-os-partner:60996 BRANCH=None TEST=Checked on gru, no more "BUG: Bad page state" error in kernel. Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087 Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/426338 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/18125 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13libpayload: Add VPD address into lib_sysinfoKan Yan
BUG=chrome-os-partner:56947 TEST=Verifed country code can be parsed from VPD in depthcharge. BRANCH=None Change-Id: I2fbbd4a784c50538331747e1ef78c33c6b8a679b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acea6e2a200e8bd78fd458255ac7fad307406989 Original-Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/425819 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13mb/lenovo/t400,x200,x201: Do not select DRIVERS_ICS_954309Arthur Heymans
This driver to configure the clock generator is not used. Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13soc/intel/skylake: Rename car_stage.S for fsp2_0Teo Boon Tiong
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S, so that it is associated with FSP driver version that is being used. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13intel/wifi: Create ACPI objects for wifi SAR configurationRobbie Zhang
To support intel wifi SAR configuration, it is required coreboot to publish two ACPI objects (WRDS and EWRD) to supply SAR limit data sets. VPD entry "wifi_sar" is required to supply the raw SAR limit data. BUG=chrome-os-partner:60821 TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot, check the SSDT dump and verify WRDS and EWRD structures. Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/17959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13google/pyro: Add ELAN touch screen supportKevin Chiu
Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18086 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13libpayload: Update ARM CrOS devices configurationPaul Kocialkowski
This updates the configuration for ARM CrOS devices (nyans and veyrons) by using the CHROMEOS Kconfig option, thus reducing the number of options to select. It also brings proper serial console support. Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/17928 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-01-13util/cbfstool: Enable adding precompressed files to cbfsPatrick Georgi
cbfstool ... add ... -c precompression assumes the input file to be created by cbfs-compression-tool's compress command and uses that to add the file with correct metadata. When adding the locale_*.bin files to Chrome OS images, this provides a nice speedup (since we can parallelize the precompression and avoid compressing everything twice) while creating a bit-identical file. Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18102 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12util/cbfstool: Add cbfs-compression-toolPatrick Georgi
cbfs-compression-tool provides a way to benchmark the compression algorithms as used by cbfstool (and coreboot) and allows to pre-compress data for later consumption by cbfstool (once it supports the format). For an impression, the benchmark's results on my machine: measuring 'none' compressing 10485760 bytes to 10485760 took 0 seconds measuring 'LZMA' compressing 10485760 bytes to 1736 took 2 seconds measuring 'LZ4' compressing 10485760 bytes to 41880 took 0 seconds And a possible use for external compression, parallel and non-parallel (60MB in 53 files compressed to 650KB on a machine with 40 threads): $ time (ls -1 *.* |xargs -n 1 -P $(nproc) -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA) real 0m0.786s user 0m11.440s sys 0m0.044s $ time (ls -1 *.* |xargs -n 1 -P 1 -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA) real 0m10.444s user 0m10.280s sys 0m0.064s Change-Id: I40be087e85d09a895b1ed277270350ab65a4d6d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18099 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12util/cbfstool: compile with -O2 by defaultPatrick Georgi
This speeds up the lzma encoder approximately four-fold. Change-Id: Ibf896098799693ddd0f8a6c74bda2e518ecea869 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-12soc/marvell/mvmap2315: Mark mvmap2315_reset() as noreturnMartin Roth
mvmap2315_reset() is called from locations where we're checking for NULL pointers. Because coverity can't tell from the code that the functions are not returning, it's showing errors of accessing pointers after we've determined that they're invalid. Mark it as noreturn, and add a loop in case the reset isn't on the next instruction. This probably isn't needed, but shouldn't hurt. Found-by: Coverity Scan #1362809 Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18103 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12sb/intel/ibexpeak: Update debug code to match other chipsMartin Roth
Other chips dump tco_status here if it wasn't handled, which makes sense. tco_sts can't be zero here, because the call would have already returned if it were. Also, dump_tco_status wouldn't print anything if tco_sts were zero. This will still only print the debug information if DEBUG_SMI is enabled in Kconfig, so in general, this change won't have much of an effect on anything. Found-by: Coverity Scan #1229598 Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18101 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-123rdparty: update arm-trusted-firmware submoduleMartin Roth
Updated to arm-trusted-firmware TOT: 236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size) 183 commits between Sep 20, 2016 and January 10, 2017 - Also add associated change to src/soc/rockship/rk3399 Makefile.inc that is required to build the M0 Firmware. Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-12sb/intel/fsp_rangeley: Fix NULL check in gpio.cMartin Roth
This should always have been an and, not an or. The only way this would happen is if no GPIOs were getting configured, so we shouldn't ever have a NULL here, but if we did, GPIOs would be randomly configured, which would have 'interesting' results. Found-by: Coverity Scan #1229633 & 1229632 Change-Id: If123372658383f84279738e1186425beba3208ca Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12google/chromeos: disable platform hierarchy on resume for TPM2Aaron Durbin
On Chrome OS devices that use TPM2 parts the platform hierarchy is disabled by the boot loader, depthcharge. Since the bootloader isn't involved in resuming a suspended machine there's no equivalent action in coreboot to disable the platform hierarchy. Therefore, to ensure consistent state in resume the platform hierarchy in the TPM2 needs to be disabled as well. For systems that resume using the firmware the platform hierarchy is disabled when utilizing TPM2 devices. BUG=chrome-os-partner:61097 BRANCH=reef TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start trunksd' shows that phEnable is 0. Change-Id: I060252f338c8fd68389273224ee58caa99881de8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18096 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-11chromeos: fix build issues within sar.cRobbie Zhang
Build issues were somehow overlooked in commit ed840023a84915ece4bc63edffef979926107d55: 1. hexstrtobin is not defined (needs the lib.h); 2. coreboot default compiler doesn't like variable initialization within for loop. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18076 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-11amd/mct/ddr3: Fix unintended sign extension warningTimothy Pearson
An unintended sign extension warning was thrown by Coverity. Explicitly state the length of the constant multiplier. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18077 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18079 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-11skylake: Do not pass VBT to FSP if display init not requiredDuncan Laurie
The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary. BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-11nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c'Arthur Heymans
Change-Id: Ib86600b687c7002646ca82d5fa52121b6eafcd60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18087 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Free malloced resources in failure branchesTimothy Pearson
Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Found-by: Coverity Scan #1347344 Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 13:56:45 +0000