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2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-29libpayload: OHCI driver correct PCI BAR readingAnton Kochkov
Correct registers base (PCI BAR) reading to be more specification friendly. Registers base only in [31-12] bits, all other proposed to be 0 but that not true for some motherboards. So adding mask to use only valid bits. Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1143 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-29libpayload: use correct types in UHCI driverAnton Kochkov
As we using 16-bit reading and writing in UHCI drive, so all variables related to that must be 16-bit too. Change-Id: Ib1abb03d054c167512e21f24f3c3da688c7fd01f Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1144 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-24X60/T60: fix mptable LINT entriesSven Schnelle
They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE. While at it, uses mptable_lintsrc() instead. Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1136 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-23Add Supermicro X7DB8 motherboardSven Schnelle
This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/493 Tested-by: build bot (Jenkins)
2012-06-23i3100: add smbus_write_byte()Sven Schnelle
Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1116 Tested-by: build bot (Jenkins)
2012-06-23Add an option for Waiting for gdb connection if the gdb stub configuration ↵Denis 'GNUtoo' Carikli
is chosen. Here's a quick demonstration on how to use it(tested on M4A785T-M). (gdb) file ./build/cbfs/fallback/coreboot_ram.debug Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done. (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyUSB0 Remote debugging using /dev/ttyUSB0 _text () at src/arch/x86/lib/c_start.S:85 85 call hardwaremain Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-22romcc: fix up attribute((unused)) detectionStefan Reinauer
The length was not accounted for correctly. Change-Id: If34f288ba9dee1cd19d60da1b9f3647b9593ac1f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1135 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-06-22libpayload: Adjust timeouts and delays in OHCI driverNico Huber
This sets the timeout for control and bulk transfers to 2s per transfer descriptor (like we set it in the EHCI driver). It also adds delays around the disabling of control and bulk list access to overcome some race conditions. Change-Id: Ia2d1db890fca51c7d9477de163d55030e0c5a04a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1127 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-22ROMCC: fix unused attribute lookupSven Schnelle
commit 57cd1dd29679918afa650c2a7e82a474765f357d added this attribute, but with wrong length, so it actually never matched. Change-Id: Ibcc7816b5fa895faa66710cc29de38f129be6a2b Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1133 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-06-22libpayload: Add check for failure in usb_attach_device()Nico Huber
This adds a simple check if a device is really configured before returning it's address to the usb hub driver who wants to attach it. Change-Id: I6fea140217c3e7468cc48ef7c3cbf2be8d11f47a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-22libpayload: Shutdown reasonably if we can't init usb msc deviceNico Huber
This lets the init of usb mass storage return if the device configuration is unusable. Also add some checks for proper shutdown so we don't free/remove an uninitialized device. Change-Id: I6daf9b38e632b6e381bcd5a7717f0f1a3150b64a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1130 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-22Teach romcc about attribute((unused))Stefan Reinauer
This makes it easier to use the same code on romcc and gcc. Specifying attribute((unused)) on romcc does nothing. Change-Id: If9a6900cad12900e499c4b8c91586511eb801987 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1132 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-06-21libpayload: Add support for interrupt transfers in OHCINico Huber
This adds support for usb interrupt transfers to the OHCI driver. Basically this enables support for HID keyboard devices. For each interrupt transfer endpoint, two queues of transfer descriptors (TDs) are maintained: the first with initialized TDs is linked to the periodic schedule of the host controller (HC), the second holds processed TDs which will be polled by the usb class driver. The HC moves processed TDs from its schedule to a done queue. We periodically fetch all TDs from the done queue, to put them on the queue associated with the endpoint, where they can be polled from. Fully processed TDs (i.e. which have gone throuch all of this) will be reinitialized and put on the first queue again. Change-Id: Iaab72c04087b36c9f0f6e539e31b47060c190015 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1128 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Fix initialization of OHCI driverNico Huber
This fixes some memory corruption, leaking and padding issues within the initialization of the OHCI driver. Change-Id: If6891f2a53e339d32c4324f4c9e0b1ed07596a60 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1126 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Implement correct done queue processing for OHCINico Huber
This adds correct processing of the done queue of the OHCI host controller (HC). We will always process the done queue after a control or bulk transfer. Unfortunately, it's hard to tell when the HC will write out the done queue, so we have do free the transfer descriptors later and have to allocate them one by one. To distinguish different types of TDs (e.g. async vs. interrupt transfers) on the done queue, they are flagged in the lsb of there .config field. We can utilize this bit for our own purpose, as it's reserved and the host controller won't interpret it and preserves its state. Change-Id: I3b2271ae6221cdd50fc0f94582afdfe52bf7e797 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1125 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Correct interchanged parameters in OHCI driverNico Huber
In ohci_private.h some invocations of a MASK macro were called with its parameters interchanged. This fixes it with the hope not to break anything nasty. Change-Id: I56cb483b208442b497dbd32ce993cc53d1fba1e5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21libpayload: Detach unresponsive usb mass storage devicesNico Huber
This enables logical detachment of unresponsive usb devices (i.e. devices not responding to control transfers) in the usb mass storage driver. Without the detection of unresponsive devices we wait way too long for the device to become ready. Change-Id: I8b8cf327f49dde25afaca4d3066f16ea86b99d3d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21libpayload: Add dummy queue heads to EHCI interrupt frame listNico Huber
This introduces a dummy queue head in the interrupt frame list of the EHCI host controller. It's a workaround for broken controllers which follow pointers from this list even if the terminate bit is set. Fortunately, they do honor the bit in queue heads and having an empty QH in the list doesn't violate the standard. The linux kernel has a similar workaround for AMD SB700, SB800, and Hudson-2/3 platforms. We observed this bug with an AMD SB600. Change-Id: Ibbb66dea5fddc89c7995a24d746bedf6bfa887be Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1124 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Add interrupt-queue underrun recovery to EHCINico Huber
If the queue of an interrupt transfer runs out, we have to reset the queue head. This also introduces the use of a spare transfer descriptor (TD) in interrupt queues, which assures, that a processed TD won't be reused until the host controller has written it back from his overlay. Change-Id: Id0eeb2808b77f1c187f164eb34bd66f8f399938b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1123 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Adjust timeout in EHCI driverNico Huber
Tested with a bunch of usb flash sticks. The slowest non-TUR (test unit ready) turn around took about 1.3s, so this commit increases the timeout to 2s. Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21i3100: Enable second IOAPIC for PCI-XSven Schnelle
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X. Add code to enable it. Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21libpayload: reg_base reading for USB EHCI driverAnton Kochkov
Added reading registers base address for USB EHCI driver in ehci_init() function. Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-21Don't use 64-bit constant 0x100000000 in linker scriptsNico Huber
The constant value 0x100000000 is used in linker scripts to calculate offsets from the end of 32-bit-addressed memory. There is nothing wrong with it, but 32-bit versions of ld do the calculation wrong. Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-20i5000: fix another typoSven Schnelle
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid. Let's do another typo fix... Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1119 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-06-20libpayload: Better error detection in USB mass storageNico Huber
This implements status transport (CSW) more closely to the standard (usbmassbulk_10). Change-Id: Ife516316e054d4e87ebe698dc487eeb9ebcfd38d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1072 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-06-20libpayload: Fix detach_contoller in the USB driverAnton Kochkov
Fixed usb controllers linked list walking in detach_controller() function Change-Id: Ia97c7ec814f75d2b1bfe185f160fb4cd32aa6fdb Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1105 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-06-20i5000: fix typosSven Schnelle
Peter and Ron pointed out two typos. They have no side effects, but it's still worth to fix them. Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1117 Tested-by: build bot (Jenkins)
2012-06-20mptable: realign comments with codeSven Schnelle
Change-Id: I4bc90334c7220512607cd5e777ce1f8cc595e2f0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1115 Tested-by: build bot (Jenkins)
2012-06-20mptable: initialize apic/bus arrays with ARRAY_SIZESven Schnelle
and increase the busses size to 32, as 16 isn't enough one some systems (i5000 for example) Change-Id: Ie09f451dd82ac25b0de85fd47807136e01da737b Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1114 Tested-by: build bot (Jenkins)
2012-06-20mptable: pretty print PCI INT entriesSven Schnelle
make it more readable by adding INT defines and a left shift. Change-Id: I7db4d8c71ab4d705833019aa4cc2f11cef7d4fee Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1113 Tested-by: build bot (Jenkins)
2012-06-20mptable: Fix BUS type determinationSven Schnelle
Change-Id: I7268b35671f6629601fa3b2a589054b8c5da5d78 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1112 Tested-by: build bot (Jenkins)
2012-06-20mptable: reindent code to comply with coreboot coding styleSven Schnelle
Change-Id: Iee27c535f56ebedaceea542c2919cde68006827c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1111 Tested-by: build bot (Jenkins)
2012-06-20mptable: Fix 'mptable.c:1019:12: warning: ‘c’ may be used uninitialized ↵Sven Schnelle
in this function' Change-Id: Icf6968f5bcbbe28c3a2a1d6ee7c1fd0be583f182 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1110 Tested-by: build bot (Jenkins)
2012-06-20mptable: remove unused variableSven Schnelle
Change-Id: I1ff7e040b5aafcdb05a3669158ae94551981e747 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1109 Tested-by: build bot (Jenkins)
2012-06-20mptable: print ioapic entriesSven Schnelle
Print IOAPIC entry based on actual data, instead of giving the user the feeling that the generated ioapic entry has any relation to reality. If the IOAPIC entry in the MPTABLE is incorrect, the user will notice it anyways. But adding a static entry (which might be also incorrect) is even worse. Change-Id: I6d0012324a9e6c7d22436ada36cbd3a4f7166f5c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1108 Tested-by: build bot (Jenkins)
2012-06-20mptable: rename LAPIC_ADDR to LOCAL_APIC_ADDRSven Schnelle
It was renamed in coreboot, so have mptable generate correct code. Change-Id: I9579209f9f47b756d8ccab63b6f942d22d53d79d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1107 Tested-by: build bot (Jenkins)
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
Those CPUs support the PECI (Platform Environment Control Interface), so enable it. This interface is commonly used for tasks like fan control. Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1104 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-06-18i5000: enforce hard resetSven Schnelle
Not doing a hard reset leaves the BOFL0 register cleared, which prevents the BSP selection from working. To make sure we start with known values, use the SPAD0 register for soft reset detection. If there's a value other than 0, do a hard reset. Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1103 Tested-by: build bot (Jenkins)
2012-06-14llshell: fix build without romccDenis 'GNUtoo' Carikli
Without that fix we have: LINK cbfs/fallback/romstage_null.debug build/generated/crt0.romstage.o: In function `ramtest': romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt' collect2: ld returned 1 exit status make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1 On the M4A785T-M which doesn't have CONFIG_ROMCC. Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1101 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-06-12Update SB800 CIMX FADTMartin Roth
- Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1055 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-06-12udelay: add missing bus frequencySven Schnelle
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1099 Tested-by: build bot (Jenkins)
2012-06-09libpayload: Add timeouts in the UHCI USB driverNico Huber
We should always have some timeout when we wait for the hardware. This adds missing timeouts to the UHCI driver. Change-Id: Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1073 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-09libpayload: Fix an integer overflow in USB mass storageNico Huber
Change-Id: I3d618497016478ea727c520e866d27dbc3ebf9af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1070 Reviewed-by: Mathias Krause <minipli@googlemail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-08libpayload: Add timeouts in the EHCI USB driverNico Huber
We should always have some timeout when we wait for the hardware. This adds missing timeouts to the EHCI driver. Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1077 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Add timeouts in the OHCI USB driverNico Huber
We should always have some timeout when we wait for the hardware. This adds missing timeouts and a more standard compliant port reset to the OHCI driver. Change-Id: I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1076 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Remove orphaned delay from OHCI USB driverNico Huber
This removes a synthetic delay of 5ms from every OHCI USB command. A delay here seems to be of no use and first tests have shown no glitches. Change-Id: Ie72b2d49e6734345708f04f3f7b86bacc7926108 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1075 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Add support for interrupt transfers in EHCINico Huber
This adds support for usb interrupt transfers in the EHCI driver. Split transactions are supported, so this enables support for HID keyboards devices over hubs in high-speed mode. Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Free intr queue structure in usb_hid_destroyNico Huber
The call to destroy_intr_queue was missing in usb_hid_destroy. Change-Id: I51ccc6a79bc005819317263be24a56c51acd5f55 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1082 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Add support for split transactions in EHCINico Huber
With split transactions, the EHCI host controller can handle full- and low-speed devices on hubs in high-speed mode. This adds support for split transactions for control and bulk transfers. Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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