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Drop dummy entry.
Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Store LID status into LIDS and change device name to LID0.
Then Intel driver can reference it.
BUG=b:151134069
TEST=check LID status by evtest
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Consistently use the official uppercase spelling.
Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ic0571d06e94708dd5e151621ab7790f3c9f775c2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.
BUG=b:151208838
TEST=build RVP successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Check for dev enabled status for CNVi and update the
UPD accordingly.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add config to override CpuRatio or setting CpuRatio to
allowed maximum processor non-turbo ratio.
BUG=151175469
BRANCH=none
TEST=Build and boot tglrvp and observe there is no extra reset
in meminit.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Palkia as a variant of Hatch.
BUG=b:150254194
BRANCH=none
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change VmxEnable UPD value based on Kconfig ENABLE_VMX
BUG=None
TEST=Built image and booted to kernel.
Change-Id: I725474643193223865a135813cf882fd7636d24a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Add template files for making a new barebones-copy of Volteer.
BUG=b:147483699
BRANCH=None
TEST=N/A
Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable GEO SAR function.
BUG=b:150347463
BRANCH=drallion
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.
BUG=b:151305120
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP
device drivers can access the parent EC device to communicate with the
EC. Also, update the Notify() call to reflect the new location of the
ECPD device.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early ec sync needs to be disabled for EFS2 to function.
BUG=b:151115320
BRANCH=none
TEST=none
Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Tigerlake platform supports Virtualization Technology for Directed I/O.
Enable VT-d feature and generate DMAR ACPI table.
BUG=None
TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI
remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and
"iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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commit 7f9ceef disables TCO SMIs unless specifically enabled, so help
the linker throw out the function that handles them in that case.
Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
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1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.
TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.
Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create new variant and build for nightfury.
BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Set value for PcieRpL1Substates according to devicetree.
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Just call get_recovery_mode_retrain_switch() directly.
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Check for dev enabled status for HDA controller and
update the UPD accordingly.
BUG=151174264
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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This adds case intrusion detection to the SMI handler. At this point one
can add the code to be executed when the INTRUDER signal gets asserted
(iow: when the case is opened).
Examples:
- issue a warning
- trigger an NMI
- call poweroff()
- ...
Tested on X11SSM-F.
Change-Id: Ifad675bb09215ada760efebdcd915958febf5778
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In case backlight control isn't enabled BCLM is zero.
Return early instead of running into a DivideByZero error.
This happens on devices that don't have backlight control, like
desktops and servers. The proper fix is to not include those
ACPI methods, but that requires a much bigger refactoring.
Change-Id: Ie9bdb00949d6d44fd99321db556d6008d2d12a7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=Verified that dmidecode produces output identical to private repo
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add LPDDR3 4GB 2133MHz SPD file.
BUG=b:149226871
TEST=Build and check cbfs has the spd.bin
Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set
"PcdDebugInterfaceFlags" UPD accordingly.
BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP UART log
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.
BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device
Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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