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2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/via/vx900: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28device/pci: Replace some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/intel/x4x: Avoid x4x.h header with romcc-bootblockKyösti Mälkki
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-28superiotool: add basic support for SCH5545Alexander Couzens
Based on the SCH5627 datasheet which is similiar SCH5545 id 0xc4, SCH5627 id 0xc6. Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28mb/google/variants/drallion: Update the spd index mapAamir Bohra
BUG=b:141575294 Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-28mb/google/drallion: Set UART for console to UART controller 0Aamir Bohra
Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is providedArthur Heymans
CONFIG_CBFS_SIZE should only be used as a parameter to generate the default FMAP. This also swaps around FMDFILE and CBFS_SIZE to avoid that the CBFS_SIZE entry disappears when filling in the FMDFILE entry below it. One advantage is that if code references CONFIG_CBFS_SIZE the jenkins buildtest will most likely fail as many boards provide an FMD file. Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-28mb/lenovo/x131e: enable mSATA slotJames Ye
Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-27mb/lenovo/x131e: correct USB port configJames Ye
Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-27fmap: Add get_fmap_flash_offset()Furquan Shaikh
CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27device: add commentary to dev_find_slot()Aaron Durbin
dev_find_slot() can sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27mb/supermicro/x11-lga1151-series: remove unneeded vendor id configMichael Niewöhner
The vendor id option set here is useless as most SSVID registers get filled with 0x8086 (their VID) by default, anyway. Besides that the Kconfig option isn't meant for retrofit ports, cf. commit 7e1c83e31bd (Add Kconfig options to override Subsystem Vendor and Device ID). The right place would be the devicetree. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If67c679bb342f63096902535734106e4f1651118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-27configs: Build test CONFIG_BOOTSPLASHPatrick Rudolph
Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35615 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27lib/bootsplash: Fix compilationPatrick Rudolph
Add missing include. Tested on Supermicro X11SSH-TF. Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26coreboot/Makefile: display error when spaces in path of toplevel makefileHimanshu Sahdev
coreboot toplevel makefile breaks when path to the coreboot directory contains spaces. This patch displays a reasonable message to the user whenever spaces are found within the path to the coreboot direcrory. This commit addresses coreboot ticket #179. Change-Id: Id11deffa01ddca1ff9332d67c7aa33a382b4cdc7 Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35434 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id codeRichard Spiegel
All solid state devices have vendor id defined by JEDEC specification JEP106, which originally allocated only 7 bits for it plus parity. When number of vendors exploded beyond 126, a banking proposition came maintaining compatibility with older vendors while allowing for 4 extra bits (16 banks) through the introduction of the concept "Continuation code", denoted by the byte value of 0x7f. Examples: 0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o 0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2 BUG=b:141535133 TEST=Build and boot grunt. Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26soc/intel/fsp_broadwell_de: move get_busno1() into vtd.cAndrey Petrov
TEST=just build it Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-26mb/supermicro: restructure x11ssh-tf to represent a x11 board seriesMichael Niewöhner
Most of the X11 boards with socket LGA1151 are basically the same boards with just some minor differences like different NICs (1 GbE, 10 GbE), number of NICs / PCIe ports etc. There are about 20 boards that can be added, if there is a community for testing. To be able to add more x11 boards easily like x11ssm (see CB:35427) this restructures the x11ssh tree to represent a "X11 LGA1151 series". There were multiple suggestions for the structure like grouping by series (x10, x11, x...), grouping by chipset or by cpu family. It turned out that there are some "X11 series" boards that are completely different. Grouping by chipset or cpu family suffers from the same problem. This is why finally we agreed on grouping by series and socket ("X11 LGA1151 series"). The structure uses the common baseboard scheme, while there is no "real" baseboard we know of. By checking images, comparing logs etc. we came to the conclusion that Supermicro does have some base layout which is only modified a bit for the different boards. X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we expect the other boards to have mostly the same device tree, there is a common devicetree that gets overridden by each variant's overridetree. Besides that some very minor modifications happened (formatting, fixing comments, ...) but not much. Documentation is reworked in CB:35547 Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26mb/mainboard/hatch: support elan touchpad for AkemiPeichao Wang
Modify IRQ pin from D21 to A21 and support wake-up from touchpad BUG=b:141519690 TEST=build bios and verify elan touchpad works fine Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26google/grunt: add new two DDR source for TreeyaPeichao Wang
new DDR particle: 1. Samung K4A8G165WC-BCWE 2. Hynix H5AN8G6NCJR-XNC BUG=b:139085024 BRANCH=master TEST=rework new source to DUT and re-flash bios to DUT and verify DUT will bring up successfully Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-26cpu/intel/: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-26cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
It is only called in ramstage. Even if it was called in romstage, execution flow is such that BSP and AP CPUs should not be able to enter update_microcode() routine concurrently. Also the Kconfig guarding the spin_lock() calls are not selected nor are the lock variables declared for these platforms. Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25util/mainboard/google: Fix hatch variant scriptEdward O'Callaghan
The script had a couple of bugs: * It didn't create the required directory under variants/ * It was treating the wildcard as literal and so couldn't find variant files to copy. V.2: Drop verbose cp && fixup wild card usage. Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-25soc/fsp_broadwell_de: fix flashconsole support for platformMatt DeVillier
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de. Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-25mb/google/kukui: Add new build target 'Juniper'Hung-Te Lin
Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKEFurquan Shaikh
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig, utility to create a new variant does not need to do that anymore in Kconfig.name Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to KconfigFurquan Shaikh
All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25Documentation/vendorcode: Add Eltan to vendor indexFrans Hendriks
Eltan is missing in the vendor index. Documentation of the eltan vendorcode is availlabe already. Add eltan to vendor index. BUG=N/A TEST=N/A Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-25mb/siemens/mc_apl1: Sort the names of all variant mainboardsWerner Zeh
Sort the names of all variant mainboards in an ascending order. Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25mb/siemens/mc_apl{2,4,5}: Enable VBOOTWerner Zeh
Enable VBOOT in Kconfig and provide a flashmap that includes all the needed sections for VBOOT support. Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to commonSridhar Siricilla
Removed mkhi_hdr structure definition from multiple SOCs, and moved to common. TEST=Built code for Hatch, apollolake boards. Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24intel/cpu: Switch older models to TSC_MONOTONIC_TIMERKyösti Mälkki
The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel: Use CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24intel/socket_mPGA604: Enable TSC_CONSTANT_RATEKyösti Mälkki
We can use intel/common implementation for tsc_freq_mhz(). Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel/common: Fix invalid MSR accessKyösti Mälkki
Fix regression from commit ecea916 cpu/intel/common: Extend FSB detection to cover TSC MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected CPU models and rdmsr() caused reset loops. Implementations deviate from public documentation. Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c to detect FSB to TSC multiplier. Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24Makefile: set TZ LANG LC_ALLAlexander Couzens
To be reproducible, TZ LANG LC_ALL should be set early in the build process to be always used. Change-Id: Iad802968347c8d41f974af930e0d0ad5b66719cb Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-24Makefile: Create the build directory before bootblock.binMartin Roth
This was causing a failure when building platforms with no bootblock when building with make -jXX Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-24Add Razer Blade Stealth (2016) H2UJohanna Schander
The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen - HDMI 2.0a via DP-1: Paradetech PS175 - AlpineRidge Thunderbolt 3 controller - TPS65982 USB-PD power switch / multiplexer Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped via IFD. The rest is left empty (0xFF). The flash is not secured in any way and can be read via flashrom. It should be the source for this port's IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch, sometimes slow to update. - Touchpad (I2C-HID) - Headphones Not part of this commit: - Thunderbolt / USB-C (Requires advanced EC signaling) - Full HDMI support (Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2019-09-24depthcharge: add CONFIG_MAINBOARD_DEPTHCHARGESelma BENSAID
CONFIG_MAINBOARD_DEPTHCHARGE is used to override the Board config for depthcharge which inherit from CONFIG_MAINBOARD_PART_NUMBER. This is mainly to avoid depthcharge config duplication. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I6cbc93ca38ad6deeca2c2fb7770024a24233b6f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-24device/mmio.h: Add bit field helpersHung-Te Lin
When accessing register with multiple bit fields, the common approach is to use clrsetbits_le32, for example: clrsetbits(&reg, (1 << 0) | (0x3 << 1) | (0x7 << 10), (1 << 0) | (0x1 << 1) | (0x5 << 10)); This hard to maintain because we have to calculate the mask values manually, make sure the duplicated shift (offset) was set correctly. And it may be even worse if the value to set will be based on some runtime values (that many developers will do a if-block with two very similar argument list), and leaving lots of magic numbers. We want to encourage developers always giving field names, and have a better way of setting fields. The proposed utility macros are: DEFINE_BITFIELD(name, high_bit, low_bit) EXTRACT_BITFIELD(value, name) WRITE32_BITFIELDS(addr, name, value, [name2, value2, ...]) READ32_BITFIELD(addr, name) Where a developer can easily convert from data sheet like BITS NAME 26:24 SEC_VIO Into a declaration DEFINE_BITFIELD(SEC_VIO, 26, 24) Then, a simple call can set the field as: WRITE32_BITFIELDS(&reg, SEC_VIO, 2); That is much easier to understand than clrsetbits_le32(&reg, 0x7 << 24, 0x2 << 24); And to extract the value: READ32_BITFIELD(&reg, SEC_VIO) That is equivalent to: (read32(&reg) & 0x3) >> 24 Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35463 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24mainboard/ocp/monolake: Hide internal NICAndrey Petrov
Disable root port IOU0 to which built-in NIC is attached. TEST=on OCP monolake, hide built-in NIC and make sure OS does not report built-in NIC Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-24soc/fsp_broadwell_de: Add devhide functionalityAndrey Petrov
Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-24emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_readHimanshu Sahdev
- configure DMA fw_cfg - add support to read using fw_cfg_dma - provide fw config version id info in logs BUG=N/A TEST=Build and boot using qemu-i440fx. Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-24mb/google/kohaku: Update DPTF parameters and TCC offset settingSeunghwan Kim
This change applies fine-tuned DPTF parameters and TCC offset setting for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet mode. BUG=b:137688474 BRANCH=none TEST=built and verified the setting values Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-24mediatek/mt8183: Use different DRAM frequencies for eMCP DDRHuayang Duan
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-23vendorcode/cavium: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23lib/trace: Replace __PRE_RAM__ useKyösti Mälkki
Change-Id: I957be92594aced2e8465e7f94d8d42e44c3418d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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