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2020-08-24libpayload: memmove: Don't make expectations of architecture memcpyJulius Werner
default_memmove() calls memcpy() when (src > dst). This is safe for the default_memcpy() implementation, but just calling memcpy() may invoke an architecture-specific implementation. Architectures are free to implement memcpy() however they want and may assume that buffers don't overlap in either direction. So while this happens to work for all current architecture implementations of memcpy(), it's safer not to rely on that and only rely on the known implementation of default_memcpy() for the forwards-overlapping case. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7ece4ce9e6622a36612bfade3deb62f351877789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24soc/amd/picasso: Add console & timestamp buffers to psp_verstageMartin Roth
Create areas for console & timestamp data in psp_verstage and pass it to the x86 to save for use later. BUG=b:159220781 TEST=Build & Boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-24mb/google/dedede/var/magolor: Add device settingsRen Kuo
Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan and Goodix touchscreen setting 3. Add user facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration BUG=None BRANCH=None TEST=build magolor firmware Change-Id: Ifc562b4a05c8955d2aec105f2f429f926ad1e702 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24soc/intel/tigerlake: Fix IPU and Vtd configRavi Sarawadi
- FSP enables IPU (Imaging Processing Unit) by default even if its disabled in devicetree. We need to fill FSP upd based on the device enablement in devicetree. - Enable Vtd IPU and IGD settings only if respective IPs are enabled. BUG=165340186 BRANCH=None TEST=IPU is disabled and doesn't show in lspci. Change-Id: Ieff57fb0ebc8522546d6b34da6ca2f2f845bf61d Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44627 Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_tableCaveh Jalali
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-24soc/intel/jasperlake: use UDK_202005_BINDINGRonak Kanabar
JSL FSP support FSP 2.2. FSP 2.2 introduces Multiphase SI init support through the FSP-S arch UPD. The FSP-S arch UPD structure is added in edk2 stable 2020 branch. Switching the support for JSL to edk2-stable202005 to intercept the FSP2.2 related support. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: Ieed1b58e491d5a89043c418f0f44f2ee9af111f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44576 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
Move a size of DDR3 SPD memory (always 256 bytes) to a common define. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24mb/asrock: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4385fded02e43f3fd8683dd926d81a59c04d3bd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24mb/pcengines: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ia1f5c22287be0d228ce1d569f3224d9d63093f3a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-24src/acpi: Drop unneeded empty linesElyes HAOUAS
Change-Id: I561717c9ee3471462ee510f12c821cfe236b23be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-24soc/sifive: Drop unneeded empty linesElyes HAOUAS
Change-Id: I20008c71d5b573d72a09068626523e10faa2d632 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-24src/arch: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ic86d2e6ad00cf190a2a728280f1a738486cb18c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24edk2-stable202005/IntelFsp2Pkg: Add FSP*_ARCH_UPD.Ronak Kanabar
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. ref: - https://bugzilla.tianocore.org/show_bug.cgi?id=2781 BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-24src/superio: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3fd0cc00f32fa073cb2a6faf2802acdbe7db592c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44614 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/dedede/variants/drawcia: add charger input current throttlingSumeet R Pawnikar
Add charger input current throttling for drawcia system BUG=None BRANCH=None TEST=Built and tested on drawcia system Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24soc/amd/picasso: Store ddr_frequency in MT/sRob Barnes
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2. BUG=b:154654737 TEST=dmidecode -t 17 matches expected speed Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24crossgcc: Upgrade MPC to version 1.2.0Elyes HAOUAS
Change-Id: I8b754c2bbb18e38d2f8619f6ac8e1544702836ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44551 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24libpayload: Cache physical location of stringsNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates the remaining pointers that are not consumed by libpayload code, all of them strings. Also update the comment that `libsysinfo` only containts physical addresses. Change-Id: I9d095c826b00d621201c34b329fb9b5beb1ec794 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of CBMEM entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to CBMEM entries that are not consumed inside libpayload code. Change-Id: I3be64c8be8b46d00b457eafd7f80a8ed8e604030 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24libpayload: Cache physical location of cb_table entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to coreboot-table entries that are not consumed inside libpayload code. Change-Id: I95cb0af151e0707a1656deacddb8a5253ea38fc3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache copy of `cb_framebuffer` structNico Huber
Our AArch64 code supports dynamic framebuffer allocation which makes it necessary to change the framebuffer information during runtime. Having a pointer inside `libsysinfo` made a mess of it as the pointer would either refer to the original struct inside the coreboot table or to a new struct inside payload space. The latter would be unaffected by a relocation of the payload. Instead of the pointer, we'll always keep a copy of the whole struct, which can be altered on demand without affecting the coreboot table. To align the `video/graphics` driver with the console driver, we also replace `fbaddr` with a macro `FB` that calls phys_to_virt(). Change-Id: I3edc09cdb502a71516c1ee71457c1f8dcd01c119 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of serial-console structNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: Icd30e95c6b8115d16dd793914fb01a1a9da1854f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical CMOS option table locationNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: I64a37bef263022edb504086c02a3fd22ce068ba4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical cbmem console addressNico Huber
Same as with other consoles and drivers that cache an address outside the payload (e.g. video/corebootfb), we should store the physical address, so we can derive the virtual address on demand. This makes it save to use the address across relocations. As a first step in migrating `libsysinfo` to `uintptr_t`, we also switch to the physical address there. Fixes the default build of FILO, tested with Qemu/i440FX and Qemu/Q35. Change-Id: I4b8434af69e0526f78523ae61981a15abb1295b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24soc/intel/common: Add downgrade support for CSE FirmwareSridhar Siricilla
Add downgrade support for CSE RW firmware. When CSE FW is downgraded, CSE may get into data compatibility issues. To avoid such issues, coreboot sends DATA CLEAR HECI command to CSE to clear CSE run time data on proactive basis during a downgrade and when CSE indicates a data mismatch error through GET_BOOT_PARTITION_INFO. BUG=b:144894771 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I0a3a3036e448e5a743398f6b27e8e62965dbff3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40561 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24util/abuild: Don't pass kconfig output through headPatrick Georgi
Closing stdout early seems to have a detrimental effect on kconfig on a system under high load (e.g. when doing lots of builds in parallel). Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-24util/abuild: Delete temporary config in failure casePatrick Georgi
Change-Id: I9b6e6b6dcfbf2b1f43c98027acae8d9af61bd6d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44624 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24cpu/x86/smm/smm_module_handler: Add x86_64 supportPatrick Rudolph
Fix compilation under x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: I2a3ac3e44a77792eabb6843673fc6d2e14fda846 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-24arch/x86/walkcbfs.S: Mark code as x86_32Patrick Rudolph
The code can only be compiled as x86_32. Mark it as such to fix errors in the x86_64 assembler. The caller has to make sure to call this code in protected mode only. Tested on HP Z220: * Still boots on x86_32. Change-Id: I4c0221fb3886b586c22fe05e36109fcdc20b7eed Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-24cpu/x86/sipi: Add x86_64 supportPatrick Rudolph
Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I916dd8482d56c7509af9ad0d3b9c28bdc48fd0b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-24mb/google/zork: Add GPIO_144 in touchscreen power on/off sequenceKane Chen
Add GPIO_144 setting to fix touchscreen function not work. 1. Modify reset pin to stop gpio delay to 200ms. 2. Reset GPIO off delay set to 1ms. 3. Add GPIO_144 as stop GPIO. 4. Stop GPIO off delay set to 1ms. 5. Set disable_gpio_export_in_crs = 1. BUG=b:160126287 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I25299861b91cb7b76e512fad743b80221e6ffb4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Fix VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS for WoomaxKane Chen
PROTO stage board version =0. EVT stage board version =1. Modify "VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS" from 2 to 1 for Woomax EVT configuration. BUG=b:165887084 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I894049298bc0313df4fe0a527c55f53ffe56dc8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23mb/google/zork: disable non-GPU HD Audio deviceFelix Held
The zork devices use the ACP (audio co-processor) and the I2S interface for audio and not the HDA (HD audio) device and interface. BUG=b:158535201,b:162302028 BRANCH=zork TEST=Equivalent change on Mandolin disabled the non-GPU HDA device with the corresponding FSP change applied. Change-Id: I6c7de881cff8398fe416151fab219142d4fc904a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23soc/amd/picasso/romstage: Set HDA disable UPD if controller disabledFelix Held
FSP has recently added support for a UPD switch to disable the non-GPU HD Audio controller. This change adds the coreboot side of the feature. To avoid having two HD Audio enable options, the value of the hd_audio_enable UPD is determined by the enable state of the non-GPU HD Audio controller in the platform devicetree. BUG=b:158535201,b:162302028 BRANCH=zork TEST=With the corresponding FSP change applied the non-GPU HD Audio device is hidden when switched off in devicetree and remains present and functional when switched on in devicetree. Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23vc/amd/fsp/picasso: add FSP-M UPD to disable the HD Audio controllerFelix Held
BUG=b:158535201,b:162302028 BRANCH=zork Change-Id: If4886591b7d73293773e4d36ec653ef42e8b2f54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44679 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23Revert "vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controller"Felix Held
This reverts commit 65605276a4cd08fd2e38f87cd80e3362265f9091. This patch shouldn't have been merged yet, since the issues on the FSP side aren't sorted out yet, so the FSP-side changes haven't landed yet. This byte will be used for an audio-related setting instead to have the audio settings grouped together. BRANCH=zork Change-Id: If79900f3a92fd949d7653001e1ca2faac7061e3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44678 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-23mb/prodrive/hermes: Add root port numbers to commentsFelix Singer
Change-Id: I06bb0493999f1f6954854f872cda46dc38930370 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-08-22mb/google/puff: Select cse_board_reset() strong symbolEdward O'Callaghan
Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. The older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset. To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly. V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common implementation instead of a local variant in mainboard.c BUG=b:162290856 BRANCH=puff TEST=none Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-22mb/google/dedede: Enable CSE Board Reset OverrideKarthikeyan Ramasubramanian
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162386991 TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-22vendorcode/google/chromeos: Introduce helper for CSE board resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset. BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-08-22drivers/spi/tpm: Add helper to get cr50 firmware versionKarthikeyan Ramasubramanian
Introduce a helper to get the cached cr50 firmware version. This information is in turn used to identify the strap configuration supported by Cr50. BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that the version cached cr50 firmware version is returned. Change-Id: Id84b152993f253878a6c133cc433a0da2c990cf2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44653 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/zork/var/ezkinil: Fix stylus GPIO to enable suspendJosie Nordrum
Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs use internal stylus and hence pen pads are configured as NC. BUG=b:164892883, b:165342107 TEST=Verified taht pen detect GPIO does not cause spurious wakes. BRANCH=None Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21superio/ite: delay PWRGD3 during resumeMichael Büchler
According to the IT8728F datasheet it is possible to add an extra delay between 3VSBSW# being set and PWRGD3 being set during resume from Suspend-to-RAM. This is enabled in the special function selection register, the default being 0. This is also useful for the IT8720F although this chip does not have the PWRGD3 output. On the corresponding pin it has PWROK2, which the setting then seems to apply to. The datasheet for the IT8720F marks the corresponding bit as reserved, but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without setting the bit, coreboot fails to resume from S3. Oscilloscope measurements have shown that setting the bit increases the delay between 3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The actual use of PWROK2 on the board design is unclear - the only destination it seems to reach is a pin header near the SuperIO marked as "GPIO1". Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-21lib: Update fmap cache error for psp_verstageMartin Roth
The assumption was that the fmap cache would be initialized in bootblock, otherwise an error is shown. This error is showing up in psp_verstage when the fmap cache is initialized there, so create a new ENV value for ENV_INITIAL_STAGE. BUG=None TEST=Boot, see that error message is gone from psp_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I142f2092ade7b4327780d423d121728bfbdab247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21soc/amd/picasso: If using VBOOT, skip the APOB_NV region for ROMartin Roth
When booting from the RO region of a VBOOT enabled ROM, there shouldn't be a reliance on anything outside of the RO section. This includes the APOB_NV region (similar to the MRC cache region). By skipping the region when setting up the BIOS Directory table, the PSP won't try to use the region when booting. The APOB_NV region is still used for the VBOOT RW sections. BUG=b:158363448 TEST=Build RO with no APOB_NV region. Dump the BDT and verify that it's not in RO, but is in RW_A & RW_B. Boot into recovery. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21util/amdfwtool: Refactor APOB_NV requirementsMartin Roth
amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21docs/purism/librem_mini: Fixup CPU model, markup linksMatt DeVillier
Change-Id: I26c0936c912490fc0ba28ee53139e3a1f3a00911 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-21mb/google/zork: provide full range backlight settings to kernelAaron Durbin
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:163583825 Change-Id: I3c337fad38e668488800f4d6bc583a82a93659d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21soc/amd/common: add rudimentary ATIF supportAaron Durbin
The Linux kenerl driver for AMD gpu currently has a floor value of 12 for brightness settings (AMDGPU_DM_DEFAULT_MIN_BACKLIGHT). AMD indicates they did this because they were concerned with certain panels flickering at lower backlight values. However, for unaffected panels it's desirable to be able to have the panel "turn off" at the lowest backlight setting. The only way to do that is to provide ATIF bindings that indicate backlight range. Option SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF is added to provide a full range for the backlight setting. If needed, this path can be built upon for fuller support, but for the time being this is the only thing necessary to make the backlight be full range. BUG=b:163583825 Change-Id: If76801a8daf6a5e56ba7d118956f3ebce74e567a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-14 03:39:18 +0000