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2018-12-05sdm845: Add SPI-NOR flash driverMukesh Savaliya
TEST=build & run Change-Id: Ie404faf37617d2ad792310709ca2063f9a372076 Signed-off-by: Mukesh Savaliya <msavaliy@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-05mainboard/google/kahlee: Add romstage GPIO initializationMartin Roth
Move the backlight initialization from bootblock to romstage BUG=b:120436919 TEST=Careena backlight is enabled Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/30039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-12-05soc/amd/stoneyridge: Run romstage mainboard code before AGESAMartin Roth
This is needed so the next patch can set up GPIOs before AGESA runs. BUG=b:120436919 TEST=Verified romstage mainboard code runs before AGESA Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/30038 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05google/sarien: Increase BIOS region to 28MBLijian Zhao
Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-05libpayload: Remove unused timer/serial driversJulius Werner
This patch removes several timer and serial drivers (and configs) that were specific to platforms which have been dropped in coreboot. Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/30029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-05soc/amd/stoneyridge: Name IO061 in ASL appropriatelyMarshall Dawson
AMD traditionally claims the resource at I/O port 61 for the onboard PC-AT speaker. In later designs, the speaker may be omitted in favor of routing the SPKR signal to the codec. Some systems implement neither, and for those it is not correct to identify the resource as a speaker. Modify the EISAID reported to the OS depending on the system design. The default is that port 61 is reported as reserved. In order to report a speaker, add #define in mainboard//dsdt.asl. TEST=check /proc/ioports and iasl -d for both ways using a Grunt BUG=b:117818432 Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/30037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-05src/(device/lib/soc): Remove unused variablesRichard Spiegel
When building grunt with flags set to detect variables that get a value but then are unused, there are 5 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. Other instances, is better to simply use the variables (one instance it's a return value, on the other instance using the variables makes code more readable). BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29985 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05mb/lenovo/x201/dsdt: Remove duplicated includePeter Lemenkov
Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05mb/lenovo/*/dsdt: Rearrange definesPeter Lemenkov
Sort mainboard-specific defines in the same order as in all other Lenovo boards. This is a purely cosmetic change which just makes diff between boards smaller. Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.aslPeter Lemenkov
Most Lenovo mainboards define their own specific defines in dsdt.asl. Let's make it consistent across all Lenovo mainboards. Tested - builds fine. Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05sb/intel/i82801{g,j}x: Remove unused smi.c filesArthur Heymans
Now that all targets featuring these southbridges use SMM_TSEG these files are unused. Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30018 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05soc/sifive/fu540: Add helper function to get tlclk frequencyJonathan Neuschäfer
tlclk is not specific to the UART block in the FU540, so let's calculate its frequency in clock.c. Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-05mb/emulation/spike-riscv: Implement mtime_initJonathan Neuschäfer
This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to the mainboard-specific directories for Spike and QEMU. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-05google/kukui: Support TPMTristan Shieh
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ, implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM interrupt. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-05mediatek: Share GPIO external interrupts (EINT) code among similar SoCsChuanjia Liu
Refactor GPIO EINT code which can be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-05soc/intel/baytrail: Implement POSTCAR stageArthur Heymans
Use common code to tear down CAR. Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05soc/intel/baytrail: Use postcar_frame functions to set up frameArthur Heymans
Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29929 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05soc/intel/baytrail: Improve CAR setupArthur Heymans
This patch does the following: - improve the style by removing tabs in front of jmp addresses - Make the code for zeroing variable MTRR more readable (copied from cpu/intel/car) - Fetch PHYSMASK high from cpuid instead of Kconfig Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05soc/intel/broadwell: Implement postcar stageArthur Heymans
This does the following: - Reuse the cpu/intel/car/non-evict CAR setup and exit. - Use postcar_frame functions to set up the postcar frame Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05smmstore: make smmstore's SMM handler code follow everything elsePatrick Georgi
Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in cpu/x86/smm.h Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05elog: make elog's SMM handler code follow everything elsePatrick Georgi
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05drivers/smmstore: Allow using raw FMAP regionsArthur Heymans
Use a raw fmap region SMMSTORE for the SMMSTORE mechanism, while keeping the initial option to use a cbfsfile. TESTED on Asus P5QC, (although it looks like the tianocore patches using it might need some love as they can't seem to save properly). Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-05soc/intel/common/lpc_lib: Add function to disable LPC Clock RunNico Huber
Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05arch/x86/include/stdint: Fix PRIu64Patrick Rudolph
We alwas define uint64_t as unsigned long long, even on x86_64. Fix PRIu64 to match the definition of the datatype, to prevent compilation errors when compiling for x86_64. Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05Documentation/mainboard/lenovo/t420.md: add pic of chipMichael Bacarella
Provide pic of the flash IC with pinouts labeled, as well as additional text about the chip. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: I9046fa63dcd4d192836417efac68ca7587ac1c91 Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Reviewed-on: https://review.coreboot.org/c/30027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-04mb/google/sarien: Enable WWAN detection on ArcadaLijian Zhao
Set GPIO D22 low to get WWAN_PERST#_R asserted. BUG=N/A TEST=Boot up with Arcada board, check WWAN get detected as USB devices through lsusb command. Change-Id: Ie848cd19fdf3b6c4b6abeb5fa3f566e5e4e7e928 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30030 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common: Limit BIOS region cache to 16MBLijian Zhao
Cache BIOS region can boost boot performance, however it can't be over 16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake), FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries. BUG=b:119267832 TEST=Build and boot up fine on whiskeylake rvp platform. Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruptionNick Vaccaro
BUG=b:111812662 TEST=flash to nocturne, boot nocturne, run "memtester 1g" and verify it passes. Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04mb/google/sarien: Define USB devices for ACPIDuncan Laurie
Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/eve: Define USB port peersDuncan Laurie
Add ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04acpi_pld: Make it easier to define the ACPI USB device groupsDuncan Laurie
The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04soc/intel/cannonlake: Add USB device namesDuncan Laurie
Add the ACPI device names for the USB ports to match what is in the DSDT so USB ports can be defined in the SSDT. Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04soc/intel/cannonlake: Increase bootblock sizeDuncan Laurie
Increase the bootblock size to 48K to match skylake. With UART enabled we are very near the 32K limit, and with upcoming changes to add USB devices in devicetree for a cannonlake board it is over the current 32K limit. Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco: Turn camera power onDuncan Laurie
Send the EC command required to turn the camera power on and verify that it shows up on the USB bus. Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable DPTFDuncan Laurie
Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco: Guard DTPF with ifdefDuncan Laurie
There is a dependency issue with the EC DPTF code accessing methods that are external, but once the mainboard includes the relevant code they become internal and the current version of IASL used by jenkins will fail to compile it. Until the new IASL is deployed everywhere wrap the EC DPTF code and expect that the mainboard will explicitly enable it. Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco/acpi: Add DPTF supportDuncan Laurie
Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29761 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04Documentation: Clarify minor detail on preparing a layout fileMichael Bacarella
The user needs to pass the original firmware image to create a layout file, not the newly compiled coreboot image. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: If47a88f06076da12d8da7a873c3e5ef64fc1f877 Reviewed-on: https://review.coreboot.org/c/30024 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04Documentation: Clarify workflow for cloning coreboot from Gerrit.Michael Bacarella
Documentation that was there seems to reference and older version. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: I3709613ae065153123d00801ea1b4ff86b100264 Reviewed-on: https://review.coreboot.org/c/30025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04Documentation: s/My/Your/ in getting started with Gerrit docsMichael Bacarella
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: I781e2d78c0525da74dd77f572839d746d3eeb3ce Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Reviewed-on: https://review.coreboot.org/c/30026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-04ec/google/wilco/acpi: Fix issues and clean upDuncan Laurie
- Disable debug output from read/write methods by default - Use argument to _REG to disable SCI when EC is unregistered - Change read/write macros to sync level 2 so they can be called when a mutex is already held - Define some missing events Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29760 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/cannonlake: Add DPTF ACPI codeDuncan Laurie
Define the constants that DPTF expects from the SOC in order to use the common DPTF ACPI code. For cannonlake this indicates the CPU device is called B0D4 and is at PCI address 00:04.0. Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29759 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common/dptf: Add method for temp conversionDuncan Laurie
Add a method to convert from 1/10 Kelvin to Celsius. This is useful for EC devices where the sensor temperature are stored in Celsius instead of Kelvin. Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29758 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common/dptf: Make CPU address a defineDuncan Laurie
In order to support using the common ACPI code on more platforms than just Apollo Lake the DPTF code needs to be told what the PCI address is for the CPU thermal device. Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Fix extended event handlingDuncan Laurie
Extended events will be handled by the OS kernel driver, but that driver needs a method exposed by ACPI to read the event data from the EC and into a buffer. Tested by generating a hotkey event and reading the buffer from the Linux kernel driver with acpi_evaluate_object(). Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29674 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Enable WiFi radioDuncan Laurie
Add EC command to enable WiFi radio and send that command at startup. Tested to ensure WiFi is functional on a sarien board. Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29673 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Enable COM1 ACPI deviceDuncan Laurie
Enable the COM1 ACPI device based on the existing Kconfig option CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to also define another value for ACPI. Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29672 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/sarien: Enable WWAN detectionAmanda Huang
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet the logic output for WWAN_PERST#_R to high. BUG=120004153 TEST=Boot up Sarien board, check WWAN get detected as USB devices through lsusb. Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04soc/sifive/fu540: Load PLL settings from a structJonathan Neuschäfer
The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29356 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04drivers/intel/fsp1_1/romstage.c: Fix typoFrans Hendriks
Correct typo of 'Initialize' BUG=N/A TEST=N/A Change-Id: I94cfd9c41bb5f9751ef4a18beaeba05108220bc8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30016 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 04:35:05 +0000