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2018-12-03nb/intel/gm45: Make fetching the blc_pwm freq its own functionArthur Heymans
Also check the EDID string using strcmp instead of strncmp. Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/lynxpoint/usb_{e,x}hci.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29932 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/dragonegg: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03include/device/smbus.h: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-03sb/intel/i82801gx: Clean up unneeded smi setup codeArthur Heymans
All i82801gx targets now use SMM_TSEG. Change-Id: Ib4e6974088a685290ed1dddf5228a99918744124 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-03nb/intel/pineview: Use common code for SMM in TSEGArthur Heymans
This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25598 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel DG41WV, resume from S3 still works fine. Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25597 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/i945: Use common SMM_TSEG codeArthur Heymans
Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. This fixes S3 resume being broken introduced by CB:25594 "sb/intel/i82801gx: Use common Intel SMM code". Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel d945gclf and Lenovo Thinkpad X60. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25595 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/i82801jx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. The platform (x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25596 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/gm45: Correctly cache TSEGArthur Heymans
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03cbmem: Enable AArch64 supportAdam Kallai
TEST=on Chromebook Kevin with 64bit userland, it works well. Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Signed-off-by: Adam Kallai <kadam@inf.u-szeged.hu> Reviewed-on: https://review.coreboot.org/c/29978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-03soc/intel/apl: Configure LPC serial IRQ modeNico Huber
Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/fsp_baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/denverton_ns: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/broadwell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/braswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29889 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29888 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/fsp_model_406dx: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29887 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/model_206{5,a}x: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29886 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/haswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications the CPU. Generate PPKG in SSDT. Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29885 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/skylake: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29884 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30sdm845: Add clock supportDavid Dai
This sets up initial clock configuration for QUP and QSPI, and includes configuration of Root Clock Generators(RCG) and clock branches enablement. TEST=build & run Change-Id: I0b1d7f6daa179c0b24a97d42b66c1a9ee596b0a3 Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30arch/power8: Rename to ppc64Jonathan Neuschäfer
POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30security/vboot: Fix remaining measured boot issuesPhilipp Deppenwiese
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30broadcom: Remove SoC and board supportPhilipp Deppenwiese
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30MAINTAINERS: Add myself as a maintainerMatt DeVillier
Add myself as a maintainer for legacy Intel-based ChromeOS devices for which I provide coreboot images as a comminuty member, and as a maintainer for Purism devices in a professional capacity. Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-30LinuxBoot: fix initramfs xz compressionMarcello Sylvester Bauer
Add the flag '--check=crc32' to the xz compression to use CRC32 for the integrity check. The linux kernel does not support CRC64 for integrity checks, which is the default flag on most xz applications. Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/c/29935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-29util/inteltool: Add Apollo Lake LPC ID and allow to read PCRsNico Huber
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL. Hence, we have to decide based on the LPC ID which device to query. Also fix a comment. Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29google/kahlee/variants/aleena: Set STAPM values.Lucas Chen
According to aleena thermal testing to set STAPM values. skin scalar for 80%. time constant for 2500s. power limit for 7.8w. BUG=b:72979852 TEST=test build for thermal check. Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part NumberLucas Chen
Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29mb/google/octopus: Create Casta variantKarthikeyan Ramasubramanian
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29mediatek/mt8183: Add DDR driver of rx dqs gating calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-29arch/acpi.h: Add some update to version 6.2aElyes HAOUAS
Some tables updated to comply with ACPI version 6.2a. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-11-29azalia: Add Azalia Reset macroLijian Zhao
Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-29{mb/cubieboard,soc/intel/quark}: Remove define __SIMPLE_DEVICE__Elyes HAOUAS
Remove the __SIMPLE_DEVICE__ define from files used only in romstage. This is not required since romstage always defines __SIMPLE_DEVICE__. Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29821 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29arch/x86/acpigen.c: Add a method to notify all CPU coresArthur Heymans
Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29882 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29arch/x86/Makefile.inc: Fix typoPatrick Rudolph
Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29mediatek/mt8183: Add MT6358 PMIC supportHsin-Hsiung Wang
PMIC provides power features like auxadc, buck/ldo, interrupt-controller..etc BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29422 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29mediatek/mt8183: Add PMIC wrapper supportHsin-Hsiung Wang
The PMIC wrapper is a proprietary hardware to connect the PMIC. This patch implements PMIC wrapper driver for the communication with PMIC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-28mb/google/kahlee: Update vBIOS used for aleenaRichard Spiegel
The aleena board uses a display that's not compatible with current VBIOS. A VBIOS specific for aleena has been merged into blobs, so modify Kconfig so that it loads the new VBIOS when building aleena, but load original VBIOS for all other boards under kahlee folder. BUG=b:112618193 TEST=Build each board under kahlee, one at a time. After each build, opened build/config.h and searched VGA_BIOS_FILE to verify that the string only changed for aleena, all other boards remained with original string. Change-Id: Iccd0853692680908d951edd142a2d8e13a561391 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-283rdparty/blobs: Add new blobRichard Spiegel
New VBIOS code has been added to blobs/mainboard/google/kahlee. It has been merged, so now coreboot needs to use latest blob. BUG=b:112618193 TEST=none Change-Id: If430ee06f03e0f20806bf8fd2b649814251ffcf5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-28drivers/intel/gma: Fix typo in headerFrans Hendriks
Correct typo of 'version' BUG=N/A TEST=N/A Change-Id: I05d7856072042c79f9d7aafdfecc9b3635f1d0cc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-28tss: implement tlcl_save_stateJoel Kitching
When an untrusted OS is running, we would like to use the Cr50 vendor-specific VENDOR_CC_TPM_MODE command to disable TPM. Before doing this, we should save TPM state. Implement tlcl_save_state for this purpose. This needs to live in coreboot codebase since on S3 resume path, depthcharge is not reached. Implement the function in both tcg-1.2 and tcg-2.0 for completeness. BUG=b:70681930,b:118202153 TEST=hack a call to tlcl_save_state into coreboot on S3 resume verify in AP console that it is called Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 Reviewed-on: https://review.coreboot.org/c/29646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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