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2019-11-10soc/intel/common/sa: Remove EBDA dependencyArthur Heymans
Saving cbmem_top across stages is not needed anymore so EBDA should not be used. The guard to cbmem_top_chipset implementation was inappropriate. Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2019-11-10lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARGArthur Heymans
All targets now have the _cbmem_top_ptr symbol populated via calling arguments or in the nvidia/tegra210 case worked around by populating it with cbmem_top_chipset explicitly at the start of ramstage, so the Kconfig guarding this behavior can be removed. Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans
Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09Kconfig: Remove untrue commentArthur Heymans
In the vast majority of cases the bootdevice is the bottleneck and compression increases bootspeed. Change-Id: Id0c11cf6d9a605d24e3148abb8d11a65d48a4529 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-09arch/x86: Replace some __SMM__ guardsKyösti Mälkki
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Avoid some preprocessor useKyösti Mälkki
Change-Id: I8daf8868af2e8c2b07b0dda0eeaf863f2f550c59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36648 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09mb/asus/p5ql-em: Add mainboardArthur Heymans
Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 800, 1067 and 1333MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure MAC address in Kconfig) - PEG slot - PS2 keyboard Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-09soc/intel/tigerlake/acpi: Copy acpi directory from icelakeSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Removed Descriptor Name for Memory mapped SPI flash and local APIC in northbridge.asl 2. Rearranged code in gpio.asl to move RBUF object under _CRS and made the file use ASL2.0 syntax. 3. Make use of absolute path for scs.asl 4. Remove unused smbus.asl 5. Rearranged code in nothbridge.asl to move MCRS object under _CRS, use absolute variable path and added TODO for further clean up. 6. Refer absolute variable path in scs.asl Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/romstage: Do initial SoC commit till romstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Add CPU/PCH/SA EDS document number and chapter number 6. Add required headers into include/soc/ from ICL directory Tiger Lake specific changes will follow in subsequent patches. 1. Add Tigerlake specific device IDs (CPU/PCH/SA) Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-08google/stout: Remove ELOG_GSMI from ECKyösti Mälkki
EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Ie0a1349ab460142dc2744155a422b5ee22528e4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08configs/config.facebook_fbg1701: Add config fileFrans Hendriks
Enable vendorcode measured and verified boot. Use VBOOT test key for VENDORCODE_ELTAN_VBOOT_KEY_FILE BUG=N/A TEST=booting Embedded Linux 4.20 kernel on Facebook FBG1701 Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08google/parrot: Remove ELOG_GSMI from ECKyösti Mälkki
EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Idf7b04edc3fce147f7857691ce7d6a0ce03f43fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08ELOG, soc/intel: Avoid some preprocessor useKyösti Mälkki
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08sb,soc/intel: Reduce preprocessor use with ME debuggingKyösti Mälkki
Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08intel/braswell: Remove duplicate set_max_freq() prototypesKyösti Mälkki
Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
Change-Id: Id56a63a67b7eb70dce6687bb9c2734a711f611b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36635 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I6ec5a33cd6a6342adfe73c050e0c376bbefad96a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08eltan/security: Remove some preprocessor guardsKyösti Mälkki
We generally let garbage-collection take care of unused functions. While at it, move some related variable declarations in to the header file and declare them const like they should be. Change-Id: I7c6fa15bd45f861f13b6123ccb14c55415e42bc7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36632 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08mb/facebook/fbg1701: Remove some preprocessor guardsKyösti Mälkki
Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08mb/google/hatch/var/akemi: disable unused USB port for Akemi platformPeichao Wang
Akemi platform dosen't support WWAN device and unused USB2 port 3, 4, 5, 7, 8 and USB3 port 3, 4, 5 so close them. BUG=None TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I7eff4da77caea7d4fe46597320be134d34d78a22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-07soc/intel/{apl,dnv,quark}: Use strip_quotes for FSP optionsMario Scheithauer
The commit 8fc523e3 (drivers/intel/fsp2_0: Use strip_quotes for cbfs filenames) breaks the Siemens APL mainboards as FSP-M never returns once it is called. The reason for this is that the -b option is missing when adding the FSP package to cbfs via cbfstool. This patch fixes this issue. TEST=tested on siemens/mc_apl5 Change-Id: I48e5fa36e1ad799d09714f53a3041f73b8ec3550 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36645 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07soc/intel/icelake: Refactor pch_early_init() codeSubrata Banik
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07lib/cbfs: Add fallback to RO region to cbfs_boot_locateWim Vervoorn
With this change cbfs_boot_locate will check the RO (COREBOOT) region if a file can not be found in the active RW region. By doing so it is not required to duplicate static files that are not intended to be updated to the RW regions. The coreboot image can still be updated by adding the file to the RW region. This change is intended to support VBOOT on systems with a small flash device. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07Rangeley: Fix incorrect BCLKKyösti Mälkki
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams <hannah.williams@dell.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07hatch: Create puff variantEdward O'Callaghan
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. V.2: Rework devicetree with comments and drop some useless gpio maps. BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-07mainboard/google: Allow Hatch variants to read SPD data over SMBusEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. V.2: Dispence with memcpy(). V.3: Revert back to previous patch with memcpy(). V.4: Rewrite again to avoid memcpy(). BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07mb/google/hatch/variants/helios: Modify touchscreen power on sequenceKane Chen
The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. from b/142368161: 1. Modify GPP_D: The specification define T1 >= 10ms. We change it to 12ms for a safety and low impact value in our mind. Enable pin as GPP_D9 is define to be AVDD in specification. Set it to 10ms to make it to be the final one to pull low during power off sequence . 2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be 500us . So we change it to 5 to be a low impact value in our mind according to the true T4 value we got . BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage ./util/abuild/abuild -p none -t google/hatch -x -a Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/x86: Create preprocessed __ROMCC__ bootblock sourceKyösti Mälkki
Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIPArthur Heymans
This is a property of the FSP, not something the user can decide. Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06soc/intel/common: Make native and FSP-T CAR init mutually exclusiveArthur Heymans
postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06drivers/intel/fsp2_0: Move Debug options to "Debugging"Arthur Heymans
Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06Kconfig: Organize debugging options per file extensionsArthur Heymans
Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36616 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06util/lint/kconfig_lint: Handle glob prefix and suffixArthur Heymans
Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-06lib: add calculate crc byte by byteXiang Wang
Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-06mb/g/drallion: Override smbios enclosure type for drallionMathew King
Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06mb/g/drallion: Consolidate 360 sensor board detectionMathew King
Create a single function to determine if the 360 sensor board is present on a device. BUG=b:143701965 TEST='emerge-drallion coreboot' Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-11-06arch/riscv: Use FDT from calling argument when using FITArthur Heymans
Only FIT payloads provide their own FDT. Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/riscv: Rename `stages.c` to `romstage.c`Nico Huber
It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06security/vboot/Kconfig: Remove unused symbolsArthur Heymans
Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-06mb/emulation/qemu: Add VBOOT supportPatrick Rudolph
Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06mainboard/google: Rework Hatch so that SPD in CBFS is optionalEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-06soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionallySubrata Banik
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other guard to assign FSP_TEMP_RAM_SIZE. Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05mb/google/hatch/variants/helios: Update TSR3 sensor thresholdsSumeet Pawnikar
Update thermal threshold settings for TSR3 sensor. There is an issue fan is always running, even during system idle state. This change fixes this issue and fan starts only when it breaches the temperature threshold. BRANCH=None BUG=b:143861559 TEST=Built and tested on Helios system Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05superio/*/*/acpi: Improve the readability of the IndexFieldElyes HAOUAS
Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-05arch/riscv: Don't link `stages.c` into ramstageNico Huber
It's superseded by `ramstage.S`. Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/common: Include Tigerlake device IDsRavi Sarawadi
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:11:41 +0000