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2020-09-14mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20WSumeet R Pawnikar
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBAnil Kumar
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Bug=None Branch=None Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/volteer: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1432491 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ife38b1450451cb25e5479760d640375db153e499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/volteer: Enable EC software syncDavid Wu
Enable EC software sync for terrador and todor BUG=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-14soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlakeShreesh Chhabbi
Selects Cache QoS mask MSR programming flow for Tigerlake SoC. BUG=b:145958015 TEST= Build and boot to Chrome OS on TGL-UP3 RVP. Recipe used: 1. Patch https://review.coreboot.org/c/coreboot/+/43494 that implements calculation of CQOS mask dynamically based on stack size usage & incorporates Tigerlake SoC specific programming flow. 2. QS Engineering Microcode based on 0x56 Official Microcode with LLC CQOS change. 3. QS SoC Part Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-13utils/docker/coreboot-sdk: Update python to python2, add python3Martin Roth
The latest debian image needs the python2 package specified instead of just 'python'. Also add python3 to the builder as we'll probably be getting python3 scripts before too long. Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-13libpayload: malloc: Fix realloc for overlapping buffersYu-Ping Wu
The current realloc() works by freeing the origin buffer, allocating a new one, and copying the data over. It's true that free() won't touch the actual memory. However, the alloc() following it will potentially modify the memory that belongs to the old buffer in order to create a new free block (right after the newly allocated block). This causes 8 bytes (HDRSIZE) to be overwritten before being copied to the new buffer. To fix the problem, we must create the header of the new free block after the data is copied. In this patch, the content of alloc() is split into two functions: 1. find_free_block(): Find a free block with large enough size, without touching the memory 2. use_block(): Update the header of the newly allocated block, and create the header of the new free block right after it Then, inside realloc(), call memmove() call right after find_free_block() while before use_block(). BUG=b:165439970 TEST=emerge-puff libpayload TEST=Puff boots TEST=Verified realloc() correctly copied data when buffers overlapped Change-Id: I9418320a26820909144890300ddfb09ec2570f43 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-13soc/amd/picasso/chip: fix typo in acp_pme_enableFelix Held
That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-13soc/amd/picasso/aoac: make AOAC device number unsignedFelix Held
The AOAC device number is never negative, so make it unsigned. BRANCH=zork Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13soc/amd/picasso/uart: make AOAC device ID in uart_enable unsignedFelix Held
This change is separate from CB:45308 to only have the directly UART- related changes in this patch train. BRANCH=zork Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13soc/amd/picasso/uart: add missing types.h includeFelix Held
BRANCH=zork Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12soc/intel/common/block/*/Kconfig: Guard options with if-blocksAngel Pons
The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols. Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected. Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12Update vboot submodule to upstream masterIdwer Vollering
Updating from commit id fefcaa65: vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path to commit id 4bb06cc1: COIL: Change denylist to blocklist This brings in 20 new commmits. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12soc/intel/denverton_ns/uart_debug: include header for uart_platform_baseFelix Held
Include console/uart.h for the declaration of uart_platform_base instead of declaring the function in the source file. Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12soc/amd/picasso/uart: make index parameters unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the check for the index to be non-negative. BRANCH=zork Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12mb/ocp/deltalake: Enable TPM2Christian Walter
Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-12cpu/intel/model_1067x: enable PECIMichael Büchler
This is required for Super I/Os to be able to read the CPU temperature through PECI. On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default. This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested workaround is "Do not initialize PECI before processor update is loaded". Since coreboot performs microcode updates before running this code it should not cause any trouble. It was tested on a Core 2 Duo E8400, stepping E0. PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium Dual-Core E2160. See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change on cpu/intel/model_6fx. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-11mb/msi/ms7721: Use PNP_IDX_EN instead of magic numberElyes HAOUAS
Change-Id: Ica66ad6da61376f64f9d24de015f84d250327d66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/ibase/mb899: Use 'PNP_IDX_*' macros instead of magic numberElyes HAOUAS
Change-Id: I1e543f8ff701fa20eaaee601ef54f0b056e61909 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/kontron/ktqm77: Use 'PNP_IDX_*' instead of magic numbersElyes HAOUAS
Change-Id: Ic4f51a59524bacb374d90c5620f810e96d7b8eb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11strongbad / coachz : Add Initial SupportBob Moragues
BUG=b:162409909 BUG=b:164196066 BRANCH=NONE TEST=Verify build of strongbad target Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbersElyes HAOUAS
Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbersElyes HAOUAS
Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11src/superio: Use 'PNP_IDX_*' macros instead of magic numbersElyes HAOUAS
Change-Id: I2f8d6d9e8b6e84bb6c2b4e73b0fbeca476130d05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/google/dedede/var/drawcia: Remove debug statement with NULL pointerKarthikeyan Ramasubramanian
The debug statement to print WiFi SAR file can potentially have a NULL pointer. Also the debug statement does not add much value. Hence remove the debug statement. BUG=b:165613510 TEST=Build and boot the drawcia board to OS. Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11sconfig: Allow to link devices to other device's driversNico Huber
Rarely, the driver of one device needs to know about another device that can be anywhere in the device hierarchy. Current applications boil down to EEPROMs that store information that is consumed by some code (e.g. MAC address). The idea is to give device nodes in the `devicetree.cb` an alias that can later be used to link it to a device driver's `config` structure. The driver has to declare a field of type `struct device *`, e.g. struct some_chip_driver_config { DEVTREE_CONST struct device *needed_eeprom; }; In the devicetree, the referenced device gets an alias, e.g. device i2c 0x50 alias my_eeprom on end The author of the devicetree is free to choose any alias name that is unique in the devicetree. Later, when configuring the driver the alias can be used to link the device with the field of a driver's config: chip some/chip/driver use my_eeprom as needed_eeprom end Override devices can add an alias if it does not exist, but cannot change the alias for a device that already exists. Alias names are checked for conflicts both in the base tree and in the override tree. References are resolved after the tree is parsed so aliases and references do not need to be in a specific order in the tree. Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11src/ec: Drop unneeded empty linesElyes HAOUAS
Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/google/dedede/var/drawcia: Add Wifi SAR for drawciaWisley Chen
drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible. Use tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:165613510 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/dedede: Enable FW_CONFIGWisley Chen
Enable FW_CONFIG and add tablet mode field in devicetree BUG=b:165613510 TEST=emerge-dedede coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/dedede: Add option to enable WiFi SAR configsWisley Chen
BUG=b:165613510 TEST=emerge-dedede coreboot Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/zork: Add woomax memory ID 0Rob Barnes
Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J. BUG=b:165611555 TEST=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11soc/amd/picasso: Fix TSC frequency calculationNikolai Vyssotski
Fix TSC frequency calculation per Picasso PPR. This code was copied from Stoney and was incorrect for Picasso. BUG=b:163423984 TEST=verify Dalboz TSC to be 1GHz BRANCH=zork Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11vc/amd/fsp/picasso: Fix FSP-S UPD header file formattingFelix Held
Use one tab instead of 8 spaces at the beginning of the lines added in commit 39a8040ddc551306d823d52a459fdb5dd717b2fe. Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-11soc/amd/common/espi_util: clarify espi_open_io_windowFelix Held
Calling espi_open_generic_io_window in espi_open_io_window depends on the condition in the preceding if statement, so move the command into an else block to make it more obvious that this is the case. TEST=Timeless build results in identical image. Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11soc/intel/tigerlake: Clean up systemagent.hSubrata Banik
List of changes: 1. Convert inconsistent white space into tab. 2. Group together all MCHBAR offset macros. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I82fc362589389081b1b1856524a972b780af9a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11device: Fix incompatible-pointer-types build errorSubrata Banik
The build error `incompatible-pointer-types` occurs while using `pci_dev_request_bus_master` as part of device ops Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11mb/google/volteer/variants/volteer2: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer2 Signed-off-by: Alex Levin <levinale@google.com> Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10trogdor: Strappings_update_final3.1_second_thisistherealone.patchJulius Werner
Apparently what I thought was lazor-rev2 is actually lazor-rev3 and nobody is really sure what lazor-rev4 is going to be at this point or how we proceed from there. What seems to be somewhat agreed upon is that for now all Lazor revisions use the "old" GPIO mapping and it's not very clear if that's ever going to change for Lazor, so let's take the revision restriction out from Lazor for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10lib/Makefile.inc: fix hex-to-bin conversion of SPD filesMichael Niewöhner
This fixes the hex-to-bin conversion command, used to generated binary SPD files from hexdumps. An issue that only appeared on one of my systems, where conversion of '01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03: for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1 00000000: 01 32 03 .2. The reason for this was that the syntax in lib/Makefile.inc is wrong, because the backslash must be escaped due to chaining two printf commands. Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10util/abuild: Remove symbols that don't exist anymore in KconfigPatrick Georgi
Bayou and OpenBIOS aren't supported by the coreboot build system anymore, so remove these mentions. Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-10soc/amd/picasso: Add MADT entry for GNB IOAPICJason Glenesk
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot will always enable the GNB IOAPIC. Cq-Depend: chrome-internal:3247431, chrome-internal:3253044 BUG=b:167421913, b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSPMarshall Dawson
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync with coreboot. Do the same for the northbridge's IOAPIC base address. Use the new values where needed, and reserve the resources consumed by the GNB IOAPIC. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10vc/amd/fsp/picasso: Sync FSP-S UPD header fileMarshall Dawson
Sync the UPD definitions with the latest auto-generated files. Definitions and usage will be updated in a subsequent FSP Integration Guide. Cq-Depend: chrome-internal:3247431 BUG=b:167421913, b:166519072, b:159664044 TEST=Boot morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10mb/google/asurada: Add config for hayatoYu-Ping Wu
BUG=b:163789704 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/mediatek: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-09-10mb/siemens/mc_apl2/gpio: Fix code styleMaxim Polyakov
Use the 96 character limit for pad macros. Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-09-10mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPOMaxim Polyakov
GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-13 14:04:30 +0000