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2019-08-23lib: hardwaremain: Call exception_init() as soon as possibleAsami Doi
Call exception_init() before calling cbmem_initialize() because ARMv8 on QEMU uses an exception handler to detect a ram size. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: If010234a6576414e7e174c075b599a4aa4c19eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/35022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-23arch/x86/acpi: Add acpi_device_hidPatrick Rudolph
Allow a driver to return device specific _HID, which will be consumed by acpigen in order to generate proper SSDTs. Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23Revert "mb/google/octopus: Disable WLAN prior the entry of S5"Kane Chen
This reverts commit 38dbd6892080c93ccd24fbfa46ed5d9bdb7d9e99. Reason for revert: ODM helped to verify w/ BT runtime suspend disabled + revert this change And issue is gone. so I revert this change see the test result in https://partnerissuetracker.corp.google.com/issues/136039607#comment32 Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-23soc/intel/cometlake: Add ISH Device IDBernardo Perez Priego
This Device ID is specific to CML, since it is obtained by reading ISH configuration RO register. In order to export ISH to kernel PCI device tree, this number must be included in list of devices supported. Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23mb/google/drallion: Add two variants - arcada_cml & sarien_cmlThejaswani Putta
These variants are to support the sarien and arcada boards with CML SOC, the drallion variant will be used to support the upcoming drallion board. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-23mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - AUO B101UAN08.3 BUG=b:139699622 TEST=builds Kodama image and working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22AGESA: Restrict use of -fno-zero-initialized-in-bssKyösti Mälkki
Only apply the flag for libagesa -class. Change-Id: Ide46214d62b2b16e5e1deaa0796be784ed813095 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34885 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22libpayload: usbmsc: Factor out usb_msc_force_init() functionJulius Werner
We're planning to have a use case with a custom USB device that implements the USB mass storage protocol on its bulk endpoints, but does not have the normal MSC class/protocol interface descriptors and does not support class-specific control requests (Get Max LUN and Bulk-Only Reset). We'd like to identify/enumerate the device via usb_generic_create() in our payload but then reuse all the normal MSC driver code. In order to make that possible, this patch factors a new usb_msc_force_init() function out of usb_msc_init() which will initialize an MSC device without checking its descriptors. It also adds some "quirks" flags that allow devices registered this way to customize behavior of the MSC stack. Change-Id: I50392128409cb2a879954f234149a5e3b060a229 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-22libpayload: usbmsc: Skip zero-length packets at end of dataJulius Werner
Some broken USB mass storage devices send another zero-length packet at the end of the data part of a transfer if the amount of data was evenly divisible by the packet size (which is pretty much always the case for block reads). This packet will get interpreted as the CSW and screw up the MSC state machine. This patch works around this issue by retrying the CSW transfer when it was received as exactly 0 bytes. This is the same mitigation the Linux kernel uses and harmless for correctly behaving devices. Also tighten validation of the CSW a little, making sure we verify the length before we read any fields and checking the signature in addition to the tag. Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34485 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22rockchip: Use new buffer_to/from_fifo32(_prefix) helpersJulius Werner
This patch changes the Rockchip SPI and I2C drivers to use the new buffer_from_fifo32()/buffer_to_fifo32_prefix() helpers when accessing their FIFOs (mostly just to demonstrate that/how the helpers work). Change-Id: Ifcf37c6d56f949f620c347df05439b05c3b8d77d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-22Add buffer_to/from_fifo32(_prefix) helpersJulius Werner
Many peripheral drivers across different SoCs regularly face the same task of piping a transfer buffer into (or reading it out of) a 32-bit FIFO register. Sometimes it's just one register, sometimes a whole array of registers. Sometimes you actually transfer 4 bytes per register read/write, sometimes only 2 (or even 1). Sometimes writes need to be prefixed with one or two command bytes which makes the actual payload buffer "misaligned" in relation to the FIFO and requires a bunch of tricky bit packing logic to get right. Most of the times transfer lengths are not guaranteed to be divisible by 4, which also requires a bunch of logic to treat the potential unaligned end of the transfer correctly. We have a dozen different implementations of this same pattern across coreboot. This patch introduces a new family of helper functions that aims to solve all these use cases once and for all (*fingers crossed*). Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-22mb/google/kukui: Add flapjack panelsHung-Te Lin
Add panels supported by flapjack. Change-Id: I547bf6f26bdbfed52a00c8cfb268d4e7c17ed889 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-22ACPI S3: Depend on RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, S3 resume path only uses memory that is reserved from OS. So there is no need for low memory backup and recovery. Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUPKyösti Mälkki
ACPI S3 resume path can only modify low memory where the non-relocatable ramstage resides, there is no need to maintain a bigger backup copy. Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mb/google/kukui: Move panel description to CBFS filesHung-Te Lin
The panel description may be pretty large (for example, 1.3k for BOE TV101) due to init commands and we should only load the right config when display is needed. BUG=None TEST=make -j; boots and see display on Krane. Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21mediatek/mt8183: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=b:135985700 BRANCH=none Test=Boots correctly on Kukui and scp can boot up normally Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21cpu/intel/car: Make stack guards more useful on C_ENV_BOOTBLOCKArthur Heymans
With C_ENVIRONMENT_BOOTBLOCK, CONFIG_DCACHE_BSP_STACK_SIZE needs to be set to define a stack region that can be shared over all stages using CAR. It makes sense to use that Kconfig option's value instead of a hardcoded value. This will result in less false positives when the stack size is big, for instance with FSP using the coreboot stack. In many configurations with C_ENVIRONMENT_BOOTBLOCK the stack_base is at the base of CAR. If the stack grows too large it operates out of CAR, typically resulting in a hang. Therefore the stack guards are extended to cover 256 bytes at the base to at least provide a warning when the romstage is dangerously close of running out of stack. Change-Id: I2ce1dda4d1f254e6c36de4d3fea26e12c34195ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-21arch/x86: Rename some mainboard_romstage_entry()Kyösti Mälkki
These platforms use different signature for this function, so declare them with different name to make room in global namespace. Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21payloads/tianocore: Enable UEFIPayloadLijian Zhao
corebootpayload package in upstream TianoCore was replaced with UEFIPayload, add external payload build option for UEFIPayload. BUG=N/A TEST=Select TianoCore payload as UEFIPayload, build and able to boot up on QEMU q35 after PCIE_BASE set. Change-Id: I0b7785fde9f4113b2cd91323ac0358b229c5a6e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34459 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21soc/intel/common/smm: Add missing printk statementTim Wawrzynczak
SMI trap handler was missing a printk statement, which caused Coverity to flag "data &= mask;" as a redundant operation. Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Found-by: Coverity CID 1381621 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-21vboot: update vboot2 functions to use new vb2_error_tJoel Kitching
To make explicit when vboot2 error codes should be returned, use the new vb2_error_t type on all functions which return VB2_ERROR_* constants. Additionally, add required vboot submodule commit id e6700f4c: 2019-07-31 14:12:30 +0800 - (vboot: update vboot2 functions to use new vb2_error_t) NOTE: This patch was merged separately on the Chromium tree: https://chromium-review.googlesource.com/c/1728499 BUG=b:124141368, chromium:988410 TEST=make clean && make test-abuild BRANCH=none Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1728292 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21Update vboot submodule to upstream masterJoel Kitching
Updating from commit id 9c906110: 2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies) to commit id a5afd01f: 2019-08-08 11:02:44 -0700 - (Minor fixes for clang) This brings in 6 new commits. Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21soc/intel/common: use PAD_BUF() inside PAD_CFG_* macrosMaxim Polyakov
Use PAD_BUF() to disable the input/output buffer inside PAD_CFG_* macros instead PAD_CFG0_RX_DISABLE/PAD_CFG0_TX_DISABLE [1] https://review.coreboot.org/c/coreboot/+/34337 Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common: gpio_defs: set trig to disable in PAD_NCMaxim Polyakov
There is no need to change the default value for the RX Level/Edge Configuration parameter if the pad is not used/connected (PAD_NC) Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21AMD fam10: Remove HAVE_ACPI_RESUME supportKyösti Mälkki
Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-21soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument "const struct device *dev" has been added to uart_lpss_init function. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML, ICL and APL platforms Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE regionTristan Shieh
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to decompress and load more data from CBFS in romstage. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mediatek/mt8183: Overlap decompressor, verstage and romstageTristan Shieh
Since SRAM space is too small to fit all needed features, enable VBOOT_RETURN_FROM_VERSTAGE and overlap decompressor, verstage and romstage to gain more space. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34871 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mediatek: Use GPIO based SPI CSYu-Ping Wu
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch changes the pinmux and binds the pins to the correponding SPIs. When using GPIO based SPI CS, we need to manually make CS log/high before/after SPI transactions. BUG=b:132311067 BRANCH=none TEST=Verified that b/132311067 is irreproducible Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21lib/bootsplash: Log bootsplash dimensions and framebuffer dimensionsJohanna Schander
The bootsplash.jpg needs to match the framebuffer resolution. Configuration errors are more visible if they can be compared easily. Changed message to be always printed: "Setting up bootsplash in ${FRAMEBUFFER_RESOLUTION}" Added message: "Bootsplash image resolution: ${IMAGE_RESOLUTION}" Change-Id: Ib4a06d53c0134b99d3e9e6d3eda9fa30fca9ef7d Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34598 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21ec/lenovo/h8: Add option to set F1-F12 as primary functionIru Cai
Tested on Lenovo ThinkPad T440p. Change-Id: I83dc2c19341475abeeacd374a1b6cf152ec9b497 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-21mb/google/kohaku: Correct DPTF temp sensor IDsSeunghwan Kim
This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessorKyösti Mälkki
Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21southbridge/intel: Tidy up preprocessor and headersKyösti Mälkki
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21vboot: use vboot2 API to set initial secdatak valueJoel Kitching
Previously, the initial value for secdatak was embedded in secdata_tpm.c as a uint8_t array. Switch to using vb2api_secdatak_create instead, and write the value in ctx->secdatak. Remove an unnecessary call to vb2api_secdata_create in _factory_initialize_tpm. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none TEST=Check that size and value of initial secdatak has not changed. Apply the patch below and check for this output: _factory_initialize_tpm():266: _factory_initialize_tpm: secdatak sizes are identical? 1 _factory_initialize_tpm():269: _factory_initialize_tpm: secdatak values are identical? 1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index ff62185107..c1818b482f 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -148,6 +148,18 @@ static uint32_t write_secdata(uint32_t index, return TPM_E_CORRUPTED_STATE; } +/* + * This is derived from rollback_index.h of vboot_reference. see struct + * RollbackSpaceKernel for details. + */ +static const uint8_t secdata_kernel[] = { + 0x02, + 0x4C, 0x57, 0x52, 0x47, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, + 0xE8, +}; + /* * This is used to initialize the TPM space for recovery hash after defining * it. Since there is no data available to calculate hash at the point where TPM @@ -250,6 +262,11 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) * indication that TPM factory initialization was successfully * completed. */ + VBDEBUG("%s: secdatak sizes are identical? %d\n", __func__, + sizeof(secdata_kernel) == sizeof(ctx->secdatak)); + VBDEBUG("%s: secdatak values are identical? %d\n", __func__, + memcmp(secdata_kernel, ctx->secdatak, + sizeof(secdata_kernel)) == 0); RETURN_ON_FAILURE(set_kernel_space(ctx->secdatak)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) @@ -452,7 +469,7 @@ uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) /* Read the firmware space. */ rv = read_space_firmware(ctx); - if (rv == TPM_E_BADINDEX) { + if (true) { /* * This seems the first time we've run. Initialize the TPM. */ Change-Id: I74261453df6cc55ef3f38d8fb922bcc604084c0a Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1652874, chromium:1655049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21mb/google/octopus/variants/bloog: Add G2Touch touchscreen supportTony Huang
Add G2Touch touchscreen support for blooglet. BUG=b:139725457 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by evtest. Change-Id: I6ebcc60f58857d8b28446932787742c2740fadd8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21chromeec: Depend on events_copy_b to identify the wake sourceRavi Chandra Sadineni
google_chromec_get_event() depends on the main copy of EC which is used by ACPI subsytem in the kernel for querying events. google_chromeec_get_event() also clears the event from EC. Thus if the kernel has to identify the wake source, it has no way to do that. Thus instead depend on events_copy_b to log the wake source. Please look at go/hostevent-refactor for more info. BUG=b:133262012 BRANCH=None TEST=Hack hatch bios and make sure hostevent log is correct. Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21mb/google/kahlee/treeya: Update Raydium TS device ACPI nodesChris Wang
Update I2C irq to EDGE trigger for Raydium TS. BUG=b:135551210 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic0a00a31eefa756b6e4ee9aac8d25c1be5ac9195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-21mb/google/kahlee/treeya: remove keyboard backlight supportChris Wang
Treeya doesn't support the keyboard backlight. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/34903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQChris Wang
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. Reference to Aleena project. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/34902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICEChris Wang
Enable ACPI TBMC notification on tablet mode change to support convertible treeya devices. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id0618c8df66267b88008dc5057892de6b530629f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Enable Synaptics touchpad andPeichao Wang
Synaptics touchscreen BUG=b:139699619 TEST=emerge-grunt coreboot chromeos-bootimage flash bios image to DUT and make sure the touchpad and touchscreen can work Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I002badd49e678e1c32c802352923ca51efb45cef Reviewed-on: https://review.coreboot.org/c/coreboot/+/35000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-20Makefile.inc, payloads: Enable -WvlaJacob Garber
Variable length arrays are dangerous, so let's make sure they don't sneak back into coreboot or any of the payloads. Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33846 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20nb/via/vx900: Ensure memory size and base are in rangeJacob Garber
We need to ensure uma_memory_size and uma_memory_base stay within a 32-bit address range. Both of these variables are 64 bits wide, so it is simplest to use 64 bit math when doing the bit shifts and then check if they are in range after. Change-Id: Idd180f31e8cff797a6499b12bc685daa993aae05 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229665, 1229666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20mb/ocp/monolake: Add IPMI CMOS clear supportJohnny Lin
coreboot would clear CMOS by request via IPMI command, for example BMC can issue "bios-util server --boot_order enable --clear_CMOS" to set the request and reboot the system, then coreboot would clear CMOS on the next boot. Tested on Mono Lake Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34857 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/hatch: Skip SD card controller WP pin configuration from FSPAamir Bohra
BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20soc/intel/cnl: Add provision to configure SD controller write protect pinAamir Bohra
Cometlake FSP allows provison to configure SD controller WP pin, As some of board design might choose not to use the SD WP pin from SD card controller. This implementation adds a config that allows to enable/disable SD controller WP pin configuration from FSP. BUG=b:123907904 Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34900 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20vc/amd/cimx/sb800: Remove old strict-aliasing workaroundJacob Garber
C strict aliasing rules state that it is undefined behaviour to access any pointer using another pointer of a different type (with several small exceptions). Eg. uint64_t x = 3; uint16_t y = *((uint16_t *)&x); // undefined behaviour From an architectural point of view there is often nothing wrong with pointer aliasing - the problem is that since it is undefined behaviour, the compiler will often use this as a cop-out to perform unintended or unsafe optimizations. The "safe" way to perfom the above assignment is to cast the pointers to a uint8_t * first (which is allowed to alias anything), and then work on a byte level: *((uint8_t *)&y) = *((uint8_t *)&x); *((uint8_t *)&y + 1) = *((uint8_t *)&x + 1); Horribly ugly, but there you go. Anyway, in an attempt to follow these strict aliasing rules, the ReadMEM() function in SB800 does the above operation when reading a uint16_t. While perfectly fine, however, it doesn't have to - all calls to ReadMEM() that read a uint16_t are passed a uint16_t pointer, so there are no strict aliasing violations to worry about (the WriteMEM() function is exactly similar). The problem is that using this unnecessary workaround generates almost 50 false positive warnings in Coverity. Rather than manually ignore them one-by-one, let's just remove the workaround entirely. As a side note, this change makes ReadMEM() and WriteMEM() now match their definitions in the SB900 code. Change-Id: Ia7e3a1eff88b855a05b33c7dafba16ed23784e43 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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