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2020-05-12Documentation/getting_started: Fix typoPaul Menzel
Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12soc/intel/skl: Drop weak mainboard_memory_init_paramsAngel Pons
We should not need that. Change-Id: Ic0181a300670ed7ee999dafedac79f3f89bfbee9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner
2020-05-12Revert "sb/intel/common/acpi: Add more Windows versions"Nico Huber
This reverts commit cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f. Advertising certain Windows versions triggers different paths in the OS. As there may also be device specific quirks in the OS, such changes need to be tested thoroughly on all affected devices. There was at least one very subtle regression introduced by this. When Linux sees "Windows 2012" support advertised, it disables the `acpi_video` backlight controls, at least on devices with Intel IGD. Without user-space handling the ACPI events, keyboard backlight controls stop working. Moreover, the commit message didn't state any reason for this change. Why was it merged? Change-Id: I722075f8e8f836b039fb8b8277e665fb49dac8f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12Revert "mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method"Nico Huber
This reverts commit b3100775ae29caebd068db8f6209561abda2fb0c. This was part of a series that moved things to common code and causes regressions. Change-Id: I239906e498c8352e6880408744f176a8aeb13dc8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12nb/intel/i440bx: Drop mainboard_enable_serial()Keith Hui
All boards using this northbridge now enable serial in bootblock, so this is no longer needed. Change-Id: I6baf2de81870dbba2a7f1abb3f1fdd6716d64511 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41048 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/common/block/lpc: Split lpc_set_spibase() into two functionsFurquan Shaikh
This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12soc/amd/common/block: Add support for common config for AMD SoCsFurquan Shaikh
This change adds support for struct soc_amd_common_config that allows multiple AMD SoCs to share common configuration. This can then be used by common/block drivers to get the required configuration from device tree. It also provides function declaration for soc_get_common_config() that needs to be provided by SoCs making use of the common configuration structure. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Idb0d797525414c99894a8e4ede65469381db7794 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Documentation/releases: Update for 4.12Patrick Georgi
Fill in some blanks for 4.12, mark it done, add template for 4.13. Also update the list of vboot supported boards. Change-Id: Id6b663f13367eb40e66af30aadd33991c8dd635c Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-12nb/intel/sandybridge: Reorder IOSAV writesAngel Pons
We only write to the IOSAV LFSR registers twice, but we do so between the writes to the other four IOSAV per-subsequence registers. Since we know that the IOSAV is sleeping when we program the subsequences, we might as well do the two oddball LFSR register writes after we have programmed the always-written-to group of four registers. That way, subsequent changes can reproducibly replace the four writes with a single macro. Tested on Asus P8Z77-V LX2, still boots. Change-Id: If7bb14a9862a53a3eba565d17401347dcc9ffbe9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40973 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12nb/intel/sandybridge: Reorder register writeAngel Pons
Reorder the order of the operands in three register writes, so that replacing them with macros in a follow-up does not change the binary. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12trogdor: Add support for rev1Julius Werner
This patch implements the pin changes needed for Trogdor rev1. Unfortunately, coreboot has to get the EC and TPM SPI busses compiled into Kconfig, so we cannot really build a single image that runs on both revisions. Introduce a Kconfig to handle this instead. Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11sc7180: clock: Add support to bump CPU levelsTaniya Das
Add support to configure the Silver and L3 PLLs and switch the APSS GFMUX to use the PLL to speed up the boot cores. Tested: CPU speed frequency validated for speed bump Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-11sc7180: Adjust memory allocations per upstream commentsT Michael Turney
Update memory regions, etc. Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11trogdor: QCSDI loading depends on VB2_GBB_FLAG_RUNNING_FAFT setting flagAshwin Kumar
Change-Id: I63f35c94bc6c60934ace5fe0fd9176443059b354 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36518 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11trogdor: Latch GPIO interrupt supportrbokka
Required for TPM IRQ. Change-Id: I8198213cf2808be5291620892185b1e534263e3f Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38714 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11trogdor: mainboard reference all QUPv3 FW driversT Michael Turney
Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37306 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11sc7180: Fix for hang during DMA transfer in SPI-NOR flash driversatya priya
Transfer sequence used by SPI-Flash application present in CB/DC. 1. Assert CS through GPIO 2. Data transfer through QSPI (involves construction of command descriptor for multiple read/write transfers) 3. De-assert CS through GPIO. With above sequence, in DMA mode we dont have the support for read transfers that are not preceded by write transfer in QSPI controller. Ex: "write read read read" sequence results in hang during DMA transfer, where as "write read write read" sequence has no issue. As we have application controlling CS through GPIO, we are making fragment bit "set" for all transfers, which keeps CS in asserted state although the ideal way to operate CS is through QSPI controller. Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7 Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39807 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11soc/amd/common/block/lpc: Reorganize LPC enable resourcesFurquan Shaikh
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC. Side-effect of this change is that the IO decode registers are written after each child device resources are considered. BUG=b:154445472 Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41070 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11soc/amd/common/block/lpc: Add config options for eSPIFurquan Shaikh
eSPI on Picasso is configured using the LPC bridge configuration registers. This change enables config options to allow SoC to select if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to select if it wants to use eSPI instead of LPC for talking to legacy devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI). BUG=b:154445472 Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11LICENSES: Fix up retained copyright linesPatrick Georgi
One author put their name on a separate line from the rest of the Copyright statement, so copy it in. Change-Id: I041bc60079a238f59bb23556a80398052744fd5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41231 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11LICENSES: retain copyright noticesPatrick Georgi
BSD and MIT style licenses require to "retain" the copyright notice. LICENSES/retained-copyrights.txt serves that purpose and was generated using: git log -p $(git grep -l "SPDX.*\(BSD\|MIT\)") |egrep -i "^-.*(copyright|\(c\).*(19|20))" | sed -e 's,^[-/#* ]*,,g' |egrep -v "(Redistributions|DISCLAIMED|PROVIDED|LIABLE|Neither|BSD-style|above copyright notice|list of conditions)" |sort -u > LICENSES/retained-copyrights.txt Change-Id: I45142b4e6acc54aeb4c8918e0367fb48e6b11604 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41222 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/nvramtool: Remove license boiler plate from DISCLAIMER file, tooPatrick Georgi
Change-Id: I7ce0f08efaddb07a5d5f484d313068e5db3c7e2e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41220 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/qualcomm/scripts: use SPDX headerPatrick Georgi
Change-Id: Ife2d84bac1973a10139db2a1489b7ea54360eee1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41219 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/cbfstool: Add SPDX header to generated linux_trampoline code, tooPatrick Georgi
Change-Id: Id84244bb0c54326ea27be8801246fdeff039fb63 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util: Use SPDX headersPatrick Georgi
Change-Id: I2858fdf74e782f425d56653491cdebe83c185d19 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11soc/intel/quark: Revamp file headersPatrick Georgi
Remove license boiler plate in favor of SPDX headers. Where there's valuable additional information, fix up formatting. Change-Id: I801f27bd1a2b9defd5672a52c3a06eb1a12a9302 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41207 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Convert more license headers to SPDX stylePatrick Georgi
Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/lint: Allow use of the HPND license groupPatrick Georgi
The Historical Permission Notice and Disclaimer (with and without permission to sell) is a BSD-style license family that OSI and SPDX consider deprecated - and yet, it's right here in our tree. Change-Id: I61624b6e54e9aba6e2f54822c1f68967c416ad3d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/lint: Also accept BSD-2-ClausePatrick Georgi
It's also GPL compatible Change-Id: I3d9243708478f315d91473009ca34786fabffda4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-11driver/i2c/max98390: Add i2c driver for Maxim 98390 codecSeunghwan Kim
Add an SSDT generator for Maxim 98390 kernel driver. Copied from 'drivers/i2c/rt1011'. BUG=b:149443429 BRANCH=None TEST=built coreboot and checked audio function with kernel patch on nightfury Change-Id: I64d776c6c9726eb5822ad4dd82f6826c2a30cb1d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39463 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Replace BSD-3-Clause and ISC headers with SPDX headersPatrick Georgi
Commands used: perl -i -p0e 's|\/\*[*\s]*Permission[*\s]*to[*\s]*use,[*\s]*copy,[*\s]*modify,[*\s]*and.or[*\s]*distribute[*\s]*this[*\s]*software[*\s]*for[*\s]*any[*\s]*purpose[*\s]*with[*\s]*or[*\s]*without[*\s]*fee[*\s]*is[*\s]*hereby[*\s]*granted,[*\s]*provided[*\s]*that[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice[*\s]*and[*\s]*this[*\s]*permission[*\s]*notice[*\s]*appear[*\s]*in[*\s]*all[*\s]*copies.[*\s]*THE[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED[*\s]*.*AS[*\s]*IS.*[*\s]*AND[*\s]*THE[*\s]*AUTHOR[*\s]*DISCLAIMS[*\s]*ALL[*\s]*WARRANTIES[*\s]*WITH[*\s]*REGARD[*\s]*TO[*\s]*THIS[*\s]*SOFTWARE[*\s]*INCLUDING[*\s]*ALL[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY[*\s]*AND[*\s]*FITNESS.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL[*\s]*THE[*\s]*AUTHOR[*\s]*BE[*\s]*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*SPECIAL,[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*OR[*\s]*ANY[*\s]*DAMAGES[*\s]*WHATSOEVER[*\s]*RESULTING[*\s]*FROM[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA[*\s]*OR[*\s]*PROFITS,[*\s]*WHETHER[*\s]*IN[*\s]*AN[*\s]*ACTION[*\s]*OF[*\s]*CONTRACT,[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHER[*\s]*TORTIOUS[*\s]*ACTION,[*\s]*ARISING[*\s]*OUT[*\s]*OF[*\s]*OR[*\s]*IN[*\s]*CONNECTION[*\s]*WITH[*\s]*THE[*\s]*USE[*\s]*OR[*\s]*PERFORMANCE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE.[*\s]*\*\/|/* SPDX-License-Identifier: ISC */|s' $(cat filelist) perl -i -p0e 's|(\#\#*)\s*Permission[\#\s]*to[\#\s]*use,[\#\s]*copy,[\#\s]*modify,[\#\s]*and.or[\#\s]*distribute[\#\s]*this[\#\s]*software[\#\s]*for[\#\s]*any[\#\s]*purpose[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*fee[\#\s]*is[\#\s]*hereby[\#\s]*granted,[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice[\#\s]*and[\#\s]*this[\#\s]*permission[\#\s]*notice[\#\s]*appear[\#\s]*in[\#\s]*all[\#\s]*copies.[\#\s]*THE[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED[\#\s]*.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*THE[\#\s]*AUTHOR[\#\s]*DISCLAIMS[\#\s]*ALL[\#\s]*WARRANTIES[\#\s]*WITH[\#\s]*REGARD[\#\s]*TO[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*INCLUDING[\#\s]*ALL[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY[\#\s]*AND[\#\s]*FITNESS.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL[\#\s]*THE[\#\s]*AUTHOR[\#\s]*BE[\#\s]*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*SPECIAL,[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*OR[\#\s]*ANY[\#\s]*DAMAGES[\#\s]*WHATSOEVER[\#\s]*RESULTING[\#\s]*FROM[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA[\#\s]*OR[\#\s]*PROFITS,[\#\s]*WHETHER[\#\s]*IN[\#\s]*AN[\#\s]*ACTION[\#\s]*OF[\#\s]*CONTRACT,[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHER[\#\s]*TORTIOUS[\#\s]*ACTION,[\#\s]*ARISING[\#\s]*OUT[\#\s]*OF[\#\s]*OR[\#\s]*IN[\#\s]*CONNECTION[\#\s]*WITH[\#\s]*THE[\#\s]*USE[\#\s]*OR[\#\s]*PERFORMANCE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE.\s(\#* *\n)*|\1 SPDX-License-Identifier: ISC\n\n|s' $(cat filelist) perl -i -p0e 's|\/\*[*\s]*Redistribution[*\s]*and[*\s]*use[*\s]*in[*\s]*source[*\s]*and[*\s]*binary[*\s]*forms,[*\s]*with[*\s]*or[*\s]*without[*\s]*modification,[*\s]*are[*\s]*permitted[*\s]*provided[*\s]*that[*\s]*the[*\s]*following[*\s]*conditions[*\s]*are[*\s]*met:[*\s]*[1. ]*Redistributions[*\s]*of[*\s]*source[*\s]*code[*\s]*must[*\s]*retain[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer.[*\s]*[*\s]*[2. ]*Redistributions[*\s]*in[*\s]*binary[*\s]*form[*\s]*must[*\s]*reproduce[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer[*\s]*in[*\s]*the[*\s]*documentation[*\s]*and.or[*\s]*other[*\s]*materials[*\s]*provided[*\s]*with[*\s]*the[*\s]*distribution.[*\s]*[3. ]*.*used[*\s]*to[*\s]*endorse[*\s]*or[*\s]*promote[*\s]*products[*\s]*derived[*\s]*from[*\s]*this[*\s]*software[*\s]*without[*\s]*specific[*\s]*prior[*\s]*written[*\s]*permission.[*\s]*THIS[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED.*AS[*\s]*IS.*[*\s]*AND[*\s]*ANY[*\s]*EXPRESS[*\s]*OR[*\s]*IMPLIED[*\s]*WARRANTIES,[*\s]*INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*THE[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY.*FITNESS[*\s]*FOR[*\s]*A[*\s]*PARTICULAR[*\s]*PURPOSE.*ARE[*\s]*DISCLAIMED.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL.*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*INCIDENTAL,[*\s]*SPECIAL,[*\s]*EXEMPLARY,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*.INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*PROCUREMENT[*\s]*OF[*\s]*SUBSTITUTE[*\s]*GOODS[*\s]*OR[*\s]*SERVICES;[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA,[*\s]*OR[*\s]*PROFITS;[*\s]*OR[*\s]*BUSINESS[*\s]*INTERRUPTION.[*\s]*HOWEVER[*\s]*CAUSED[*\s]*AND[*\s]*ON[*\s]*ANY[*\s]*THEORY[*\s]*OF[*\s]*LIABILITY,[*\s]*WHETHER[*\s]*IN[*\s]*CONTRACT,[*\s]*STRICT[*\s]*LIABILITY,[*\s]*OR[*\s]*TORT[*\s]*.INCLUDING[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHERWISE.[*\s]*ARISING[*\s]*IN[*\s]*ANY[*\s]*WAY[*\s]*OUT[*\s]*OF[*\s]*THE[*\s]*USE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE,[*\s]*EVEN[*\s]*IF[*\s]*ADVISED[*\s]*OF[*\s]*THE[*\s]*POSSIBILITY[*\s]*OF[*\s]*SUCH[*\s]*DAMAGE.[*\s]*\*\/|/* SPDX-License-Identifier: BSD-3-Clause */|s' $(cat filelist) $1 perl -i -p0e 's|(\#\#*) *Redistribution[\#\s]*and[\#\s]*use[\#\s]*in[\#\s]*source[\#\s]*and[\#\s]*binary[\#\s]*forms,[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*modification,[\#\s]*are[\#\s]*permitted[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*following[\#\s]*conditions[\#\s]*are[\#\s]*met:[\#\s]*[*1. ]*Redistributions[\#\s]*of[\#\s]*source[\#\s]*code[\#\s]*must[\#\s]*retain[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer.[\#\s]*[*2. ]*Redistributions[\#\s]*in[\#\s]*binary[\#\s]*form[\#\s]*must[\#\s]*reproduce[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer[\#\s]*in[\#\s]*the[\#\s]*documentation[\#\s]*and.or[\#\s]*other[\#\s]*materials[\#\s]*provided[\#\s]*with[\#\s]*the[\#\s]*distribution.[\#\s]*[\#\s]*[*3. ]*.*used[\#\s]*to[\#\s]*endorse[\#\s]*or[\#\s]*promote[\#\s]*products[\#\s]*derived[\#\s]*from[\#\s]*this[\#\s]*software[\#\s]*without[\#\s]*specific[\#\s]*prior[\#\s]*written[\#\s]*permission.[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*ANY[\#\s]*EXPRESS[\#\s]*OR[\#\s]*IMPLIED[\#\s]*WARRANTIES,[\#\s]*INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*THE[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY.*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.*ARE[\#\s]*DISCLAIMED.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL.*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*INCIDENTAL,[\#\s]*SPECIAL,[\#\s]*EXEMPLARY,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*.INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*PROCUREMENT[\#\s]*OF[\#\s]*SUBSTITUTE[\#\s]*GOODS[\#\s]*OR[\#\s]*SERVICES;[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA,[\#\s]*OR[\#\s]*PROFITS;[\#\s]*OR[\#\s]*BUSINESS[\#\s]*INTERRUPTION.[\#\s]*HOWEVER[\#\s]*CAUSED[\#\s]*AND[\#\s]*ON[\#\s]*ANY[\#\s]*THEORY[\#\s]*OF[\#\s]*LIABILITY,[\#\s]*WHETHER[\#\s]*IN[\#\s]*CONTRACT,[\#\s]*STRICT[\#\s]*LIABILITY,[\#\s]*OR[\#\s]*TORT[\#\s]*.INCLUDING[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHERWISE.[\#\s]*ARISING[\#\s]*IN[\#\s]*ANY[\#\s]*WAY[\#\s]*OUT[\#\s]*OF[\#\s]*THE[\#\s]*USE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE,[\#\s]*EVEN[\#\s]*IF[\#\s]*ADVISED[\#\s]*OF[\#\s]*THE[\#\s]*POSSIBILITY[\#\s]*OF[\#\s]*SUCH[\#\s]*DAMAGE.\s(\#* *\n)*|\1 SPDX-License-Identifier: BSD-3-Clause\n\n|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11treewide: split off license text, remove extra copyright noticesPatrick Georgi
Copyright notices are best stored in AUTHORS Change-Id: Ib9025c58987ee2f7db600e038f5d3e4edc69aacc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41203 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util: Add SPDX header, replacing boiler plate where applicablePatrick Georgi
In a few cases a license was added: Stuff coming from Linux is "GPL-2.0" (not GPL-2.0-only!), build-release is by me and got the usual GPL-2.0-only treatment. uio_usbdebug and spkmodem had their licenses propagate to all their files. Change-Id: Ia5712bbaa417cb9e937834512351fcc0acfa16be Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41202 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util: Fix up a few comments after the "file is part of the" removalPatrick Georgi
Change-Id: I930739bea705988181b2e60f30516f4a7cb5c82d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41197 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/nvramtool: Remove "this file is part of" linesPatrick Georgi
As requested by Stefan. For nvramtool some of these lines are part of a paragraph of fluff, so manual processing was easier than adapting the script used for the rest of the tree. Change-Id: Id52c4c264cded0582a97da131b695a046cbd67c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-11util/lint: Omit more vendorcode from license header testPatrick Georgi
This is all code coming from the outside, so let's keep these files untouched as much as possible. A couple of files is added to the list by name because their license, while free, can't be properly modelled in SPDX: - lzmadecode is (LGPL OR CPL) WITH special-exception - stack.c and start16 are some weird (but free) US Gov't license grant - two XGI related files have "BSD except for Linux, where it's GPL" Change-Id: I42dec503b9c427a66792d3fec99ca8df1a360e47 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11Documentation/4.12-relnotes.md: Add a note about unit testing corebootJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Id6365b86640832b91a722cd12f64c03fc8a41fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-11mainboard/asus/p3b-f: Reintroduce as variant of p2bKeith Hui
Fold this last ASUS 440BX board into the P2B family, while bringing in some changes: - Devicetree becomes overridetree. - Remove non-existent IR device and disable ACPI device on Super I/O to match OEM firmware. - Add SB GPO settings from OEM firmware to devicetree. This disables the SPD enabling magic this board needs. By moving the enabling part to bootblock the hacky enable_spd hook can be eliminated. - Initialize the serial port in bootblock, like the other boards. Boot tested on hardware. Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/cyan/*: fixup GPIOsMatt DeVillier
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This was partially reverted in a86bbea0 [google/cyan: set touchscreen GPIO to non_maskable], but did not resolve all of the issues. Additionally, 73b723d also accidentally changed the pad interrupt select from L3 to L1 for all touchscreen GPIOs. Clean up this mess by setting all touchpad/touchscreen GPIOs back to maskable, and set the pad level to L3 for all touchscreen GPIOs. Tested on several cyan variants Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11soc/intel/skylake: Allow setting of PcieRpMaxPayloadWim Vervoorn
Add setting of the MaxPayload for each root port from the device tree. By default MaxPayload is set to 128 bytes. This change allows changing to 256 bytes. BUG=N/A TEST=tested on facebook monolith Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-11superio/winbond/w83977tf: Only list IR logical device if neededKeith Hui
Really old versions of W83977TF Super I/O had an IR logical device, but is no longer the case. It does not exist in the newer W83977EF version, installed in some Asus P2B family boards, and served by this same code. Add a config option on the off chance we may see board with it (as if we would) and don't include this device unless it is set. Saves us from the need to declare a not-present device off and/or extraneous PNP device errors about a not-present device. Change-Id: I761ebc41f1735a03e768339a68ca139167edc095 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41004 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-113rdparty/libgfxinit: Update submodule pointerMatt DeVillier
Update libgfxinit submodule pointer to pull in workaround for VT-d. Change-Id: I09f811bdb917365f4e97b7ab385781337d4c9cf7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/octopus/variants/dood: Disable XHCI LFPS power managementKenneth Chan
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2020-05-11soc/sifive/fu540: Add missing '#include <commonlib/bsd/helpers.h>'Elyes HAOUAS
This is used for 'KHz' (line #19) Change-Id: I4d610607b50d2fac1150deaaf94f3cb331540fbc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-11soc/intel/tigerlake: Update C-State infoWonkyu Kim
C-State latency table was exposed by both intel-idle driver and BIOS/coreboot. And table in Kernel was used before. After kernel patch (https://patchwork.kernel.org/patch/11290319/), only BIOS/coreboot exposes C-State latency table through _CST. As current C-State latency table info is not correct for Tigerlake, update proper info according to BWG and reference code. - Update latency: CpuPowerMgmt.h Use BIOS reference code as values in BWG is not up-to-dated - Remove MSR program for latency: BWG 4.6.4.3.4 Reference: - TGL BWG #611569 Rev 0.7.6 - https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h BUG=b:155223704 BRANCH=None TEST=Boot to OS and check C-State latency expected result >cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency} POLL C1_ACPI C2_ACPI C3_ACPI 0 1 253 1048 For detail, refer Bug info. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-05-11mb/intel/jasperlake_rvp: Turn off unused I2C lanesPandya, Varshit B
Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-11mb/intel/jasperlake_rvp: Add support for SMI handlerMaulik V Vaghela
SMI handler was not present in jasperlake rvp to handle wake events when platform goes to sleep or shutdown or s0ix. Adding this support for board which supports chromeec. BUG=None BRANCH=None TEST=Check wake event on board and platform wakes up due to events lid wake event or power button press. Change-Id: I8e35955b06d6efaf9275ec03f519c9bcaa9ba345 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-11mb/google/kukui: fix screen scrolling on devices using anx7625Paul Ma
anx7625 enables MIPI receiver to check EOTP packet as default. If MIPI_DSI_MODE_EOT_PACKET is not set in flags, soc dsi will not send out EOTP packet and some panel models will display abnormal such as scrolling all the time. BUG=b:144824303 BRANCH=kukui TEST=boot damu board, edp panel with anx7625 as bridge boots up without scrolling. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41161 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/kukui: Fix backlight flash white before show logoJitao Shi
Turn backlight off before panel poweron. BUG=b:155107047 TEST=make # board = kukui BRANCH=kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41146 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 09:22:01 +0000