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2020-06-22cpu/x86/smm: Use already defined APM_CNT messagesKyösti Mälkki
Change-Id: Ie9635e10dffe2f5fbef7cfbd556c3152dee58ccc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22soc/intel/broadwell/systemagent.c: Fix typoAngel Pons
Broadwell does not have any `TESGMB`, but it has a `TSEGMB`. Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22nb/intel/haswell: Use 16-bit ops on PCI COMMANDAngel Pons
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops to update it. Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22mb/google/hatch: Stop AP power-off on Puff & variants cr50 updatesEdward O'Callaghan
Fix Puff and its variants to not shutdown the AP before the cr50 reboot. This is the same approach that Sarien do to remain on during a cr50 cycle. BUG=b:154071064 BRANCH=none TEST=none Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Make puff and variants share common dptf.aslEdward O'Callaghan
Here we consolidate some of the dptf.asl duplication between Puff and it's variants. Customizations can be done later either as a direct copy or preferably via introducing a #define. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-22mb/google/hatch: Make puff and variants share common ec.hEdward O'Callaghan
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-21mb/protectli/vault_kbl: Enable Intel PTTMichał Żygowski
TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-21src: Substitute `__FUNCTION__` with `__func__`Angel Pons
The former is not standard C, and we primarily use the latter form. Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-06-21amd/mandolin: unbreak SeaBIOS VBIOS supportFelix Held
Commit 86ba0d73f34185533e5e2d4258aa3bf3dba40ed4 added VBIOS support for Raven2 silicon and changed the VBIOS file names to the format including the PCI device revision number. Upstream SeaBIOS expects the file to have only the PCI vendor and device IDs in the CBFS file name, so it doesn't find the VBIOS any more after that patch got applied. This patch adds the path and CBFS file name to include the Picasso VBIOS a second time under the CBFS file name SeaBIOS expects. This is a workaround and not a clean solution, but avoids breakage. It's separated from the rest of the Mandolin support, so it can just be reverted after a proper fix is implemented. https://chromium-review.googlesource.com/2015963/ in combination with a links file in CBFS might solve the issue for most of the cases, but it's not sure yet if for all, so a proper fix might require more than that. BUG=b:153675508 Change-Id: I4d9042615965b6a2d9255c194cf23368264ffe54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42433 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-21mb/amd/mandolin: Add Picasso CRBFelix Held
Mandolin is the CRB for AMD Picasso and Dali. The mainboard code still needs a little cleanup and verification, but I'll do that in a follow-up to have a non Chromebook board using the Picasso SoC code in tree as soon as possible to be able to detect some possible breakage. BUG=b:130660285 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20vc/google/chromeos/elog.c: Clean up codeAngel Pons
Constify local variables and drop redundant logic, while preserving the original behavior. While we are at it, also reflow print statements. Change-Id: Id024f3ac717dad98c4287add9b33defde7a0028d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-20mb/google/jecht: Correct hda_verb mic pin configsMatt DeVillier
Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot guado variant, verify mic attached to 3.5mm jack functional Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42518 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/beltino/**/hda_verb.c: Correct mic pin configsMatt DeVillier
Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot panther and zako variants, verify mic attached to 3.5mm jack functional Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42499 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20ACPI: Drop some HAVE_ACPI_RESUME preprocessor useKyösti Mälkki
Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-20mb/google/zork: rename fch_apic_routing struct to fch_irq_routingFelix Held
fch_apic_routing is used as name of an array that init_tables() populates with the APIC IRQ routing information. Also the fch_pirq array where fch_apic_routing was used as struct name contains the IRQ mapping for both PIC and APIC mode, so rename it to fch_irq_routing. Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-20mb/google/zork: remove redundant IRQ routing configurationFelix Held
The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in init_tables(), so the fch_pirq table entries where both IRQ numbers are set to fch_pirq are redundant and can be removed. Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19soc/intel/tigerlake: Update TCSS for SW CM supportJohn Zhao
This change adds support for SW CM. Add Operating System Capabilities (_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet Protocol tunneling and enable PCIe tunneling as well. Remove Connect Topology(CNTP) command because kernel driver directly works with SW CM Thunderbolt firmware. Update _DSD method for USB4 support across XHCI and PCIe root ports. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-193rdparty/blobs: advance submodule pointerFelix Held
Changes in 3rdparty/blobs: * Update of the OCP Tiogapass Flash descriptor binary * Move binary policy as README.md * Markdownify README.md * Add APCB binary for AMD Mandolin Change-Id: I0c45969626f30dca42bba1f137e85ec0999fc671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-19mb/google/zork: Disable UART 1, 2 and 3Raul E Rangel
We don't use these on zork, so lets save the power. BUG=b:153001807 TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain powered off. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-19soc/intel/common/acpi: rename dptf.asl to dptf_common.asl fileSumeet R Pawnikar
Rename dptf.asl to dptf_common.asl under soc/intel/common/acpi path to avoid any kind of confusion with another dptf.asl file under soc/intel/common/acpi/dptf path. Sometime it's confusing to have two dptf.asl files just one directory apart. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I23d93719e23c0b7659ccb23e5d0868f879bc162c Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms and update volteer speficic dsdt.asl file accordingly. The Linux kernel driver expects these new acpi device ids for dptf functionalities. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19soc/amd/picasso/uart: factor out console-related functionsFelix Held
Move uart_platform_base and uart_platform_refclk to their own compilation unit to avoid preprocessor usage. The newly created compilation unit is only added to the build when PICASSO_CONSOLE_UART is selected. Change-Id: I56911addc8c000a0772156e5166720867cdd26fe Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19vc/amd/fsp/picasso: Use fixed width fields for platform descriptorsMatt Papageorge
PCIe platform descriptors passed to Picasso FSP should use fixed width fields. BUG=b:153681134 TEST=Boot system and suspend/resume. All PCIe devices train succesfully. Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Change-Id: If2a34be895db2c19c8830f5888cb99e43ad21b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42519 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-19mb/*/*/Kconfig: guard board name in quotesPatrick Georgi
New kconfig dislikes unquoted slashes. Change-Id: Ief242de081071021b9c904a24535d025f6674270 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19mb/pcengines/apu2: Update GPIO Reads & writesMartin Roth
The APU2 was using the soc/amd/common functions to do GPIO reads and writes. The functions that were being used are getting eliminated in the SOC directory, but since the APU isn't using the rest of that code (as it's not using the rest of the SOC codebase), it proved to be problematic to use the updated functions. The solution I've put in place here is to pull everything needed for the GPIO reads & writes into the gpio_ftns.c & h files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ied39c114bdf3637977d21f56fd7db428c52e4706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-06-18src/device/Kconfig: Introduce WANT_LINEAR_FRAMEBUFFERAngel Pons
This decouples the linear framebuffer type from the symbols needing it. Change-Id: I733e630e0aa2fb2947d079caef26253ce443fe91 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42432 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/amd/picasso/i2c: use config_of_soc()Felix Held
Change-Id: I2ebe072a5c887b16d2a39f029069bc8674f8eaea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18soc/amd/picasso/acp: use config_of_soc()Felix Held
Change-Id: I815b013438d66eef6605dba7cfbd96b9a4aff9b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-18soc/amd/picasso: Add ability to enable/disable UART to device treeRaul E Rangel
If we are not using the UARTs or they don't have the correct GPIOs configured we should let the mainboard disable them. BUG=b:153001807 TEST=Dump SSDT and see UART device is disabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-18soc/amd/picasso: remove AMDFW_OUTSIDE_CBFS optionFelix Held
The option to have amdfw outside of CBFS used dd to write amdfw at a given location overwriting anything that was there before, which may cause the build to fail due to the FMAP header being overwritten resulting in a not too obvious error that the image is a legacy image without FMAP header. Mandolin was the only board using this functionality, but I fixed the placement of components in the flash image there, so that amdfw can just be placed in CBFS avoiding those problems. Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18lib/hardwaremain: Drop HAVE_ACPI_RESUME guardsKyösti Mälkki
Header was moved outside arch/. Change-Id: I1f2f0d96d49b5d921f77512ad5e2bf3f60adb484 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18ACPI,drivers/: Do not guard <acpi/acpi.h>Kyösti Mälkki
Header was moved outside arch/. Change-Id: Id96c2bdcee49cddab6610c7e2cd6f07638279256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18ACPI: Clean up some S3 related leftoversKyösti Mälkki
With RELOCATABLE_RAMSTAGE the backing up of low memory on S3 resume path was dropped. We forgot some things behind. Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18soc/intel,chromeos: Fix EC RO/RW status in GNVSKyösti Mälkki
For baytrail and braswell, explicitly initialise it to ACTIVE_ECFW_RO without ChromeEC. For broadwell and skylake, fix it to report actual google_ec_running_ro() status. Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18mb/bap/ode_e21XX: Drop left over unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Idd907311dde187aa62d29a9d3943b6d5c08a1f71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-18soc/intel/tigerlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~25 ms for an extra overhead of ~1KiB. LZ4 Compression: fsps.bin 0xe6fc0 fsp 254262 LZ4 (290816 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 712,361 (1,072) 18:finished LZ4 decompress (ignore for x86) 750,695 (38,334) LZMA Compression: fsps.bin 0xe6fc0 fsp 253415 LZMA (290816 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 707,696 (1,150) 16:finished LZMA decompress (ignore for x86) 767,763 (60,067) BUG=b:158034451 TEST=Build and boot volteer mainboard. Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel/jasperlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~50 ms for an extra overhead of ~1.5 KiB. LZ4 Compression: fsps.bin 0xa9fc0 fsp 203423 LZ4 (262144 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 433,550 (1,154) 18:finished LZ4 decompress (ignore for x86) 461,620 (28,069) LZMA Compression: fsps.bin 0xa9fc0 fsp 202132 LZMA (262144 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 478,448 (1,174) 16:finished LZMA decompress (ignore for x86) 557,725 (79,277) BUG=b:158034451 TEST=Build and boot waddledoo mainboard. Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/cannonlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZMA compression technique to compress FSP-S. This provides some SPI ROM space savings(~27 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZMA is chosen over LZ4 since it provides extra space savings of ~1 KiB for the decompression overhead of ~7 ms. LZMA Compression: fsps.bin 0xd1fc0 fsp 190132 LZMA (217088 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 343,289 (417) 16:finished LZMA decompress (ignore for x86) 373,922 (30,632) LZ4 Compression: fsps.bin 0xd1fc0 fsp 191310 LZ4 (217088 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 345,676 (581) 18:finished LZ4 decompress (ignore for x86) 369,101 (23,424) BUG=b:158034451 TEST=Build and boot helios mainboard. Change-Id: Ic0d0d81c81eaa365f3dbfdd2e00ac76cea287387 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42446 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18vendorcode/intel/fsp: Update MemInfoHob header for Jasper LakeAamir Bohra
Jasper Lake has been using the incorrect MemInfoHob header. Updating the header to align it with Jasper Lake MRC code. BUG=b:158722318 TEST=Verify memory info is populated for channnel 0 and 1 on wadddledoo. Change-Id: Icca3e3b4cda9ca257f3b725823facf52ceec37b7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-18mb/google/dedede: Add support for 16 MiB flash map descriptorKarthikeyan Ramasubramanian
Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18lint: convert checkpatch_json.py to python 3Stefan Reinauer
Align all coreboot scripts on one python version. Tested by running the original suggested test: $ nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl \ --no-signoff -q - | tee checkpatch.txt $ util/lint/checkpatch_json.py checkpatch.txt \ comment.json checkpatch.txt Change-Id: Iec2bb0be23b27a3eaf92f293c962a8e6bfb03af0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-06-18soc/intel: remove unused dptf.asl file and other definesSumeet R Pawnikar
Remove unused cannonlake dptf.asl file and cleanup defines from apollolake dptf.asl file as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18mb/google: remove cannonlake dptf.asl include file from dsdt filesSumeet R Pawnikar
Remove cannonlake dptf.asl include file from all the dsdt files as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/common: make dptf acpi device ids configurableSumeet R Pawnikar
Make dptf acpi device ids configurable for thermal functionality as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I5161d19dc663cdb9a7b004bb681059c9af2aaf4f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18mb/google/hatch: fix variants' selection of CHROMEOS_DSM_CALIBMatt DeVillier
CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if CHROMEOS already selected, otherwise building for non-ChromeOS targets fails. Test: build HELIOS for non-ChromeOS target (Tianocore payload) Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google/volteer/variants/terrador: Disable EC SW syncDavid Wu
It is the reference board of TGL-Y platform, we want to disable EC SW sync for Proto stage, it would be re-enabled before EVT stage. BUG=b:156435028 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18MAINTAINERS: Organize contentsAngel Pons
Group entries by categories, and sort the groups alphabetically. Also, separate different mainboard vendors with two extra spaces for clarity. Change-Id: I43df8c24a40433357760827777497cbac4b6a919 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18soc/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Fix last legacy ASL syntax match in acpi/pcr.asl BUG=none TEST=Deltan coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia1021851b42b8fad52b3197d9003056d3dd2db04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42437 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 15:31:27 +0000