summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-04-10rockchip: support displayhuang lin
Implement VOP and eDP drivers, vop and edp clock configuration, framebuffer allocation and display configuration logic. The eDP driver reads panel EDID to determine panel dimensions and the pixel clock used by the VOP. The pixel clock is generating using the NPLL. BUG=chrome-os-partner:31897 TEST=Booted Veyron Pinky and display normal BRANCH=None Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853 Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: select VIRTUAL_DEV_SWITCHDavid Hendricks
Like most newer Chromebooks, Pinky and Jerry do not have physical dev switches. BUG=chrome-os-partner:33395 BRANCH=none TEST=built and booted on Pinky, crossystem prints a valid value for devsw_cur instead of an error. Change-Id: If97ffa6f99eb31c05915f3ee82aaf6bd252d29e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db302d7286d3e7df9442928dac1d611a2c103163 Original-Change-Id: I186518a59699d293c7938221b3ae45b27361c255 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229680 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Adapt to new board revisionsJulius Werner
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the power button GPIO changed polarity to low, the 5V_DRV pin for USB power was moved to the AP again (welcome back!), and the EMMC_RST_L is now finally on a port with the right IO voltage so we don't need any weird pull-up tricks anymore. Since there are very few Jerry rev1s around, we'll just move it over to the new code directly without introducing board ID differences (also, because I have no idea how they stuffed it this time... is this one actually called rev2?). BRANCH=None BUG=None TEST=Still boots on my Pinky rev2, though that doesn't say much. Change-Id: Id11044cedcaac5a4ae07e696893823925107a6db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55344a9518ff04edcef01bcd40817e9e4b613717 Original-Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229010 Original-Reviewed-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Port CPU overshoot preventionJulius Werner
This patch ports commit 567f616f (rk3288: slowly raise to max cpu voltage to prevent overshoot) to Veyron_Jerry. It also fixes include ordering and some comment grammar in the affected code. BRANCH=None BUG=chrome-os-partner:32716 TEST=None Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942 Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228938 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: sdram_get_ram_code() -> ram_code()David Hendricks
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Original-Reviewed-on: https://chromium-review.googlesource.com/227249 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: use gpio_base2_value() in board_id()David Hendricks
This makes board_id() use the generic gpio_base2_value() function to obtain the value of the board ID straps. BUG=none BRANCH=none TEST=tested on pinky Change-Id: I15c1310889b989c34638fd342011aef5fe7bcec1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcbb8a6998a66531326afe16b232395d49fee64d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I5847bf1c5b26bcaf7d36103f31bb255b31ff8185 Original-Reviewed-on: https://chromium-review.googlesource.com/228370 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5VJulius Werner
LDO7 (VCC10_LCD_PWREN_H) is essentially just a glorified GPIO that turns the real VCC10 regulator on or off. We tried setting it to 3.3V since it matches the VCC33_SYS voltage on the input of that regulator. However, we didn't notice that the LDO only supports going up to 2.5V. This patch changes the voltage to the allowed maximum, which should still work fine as an enable line (and is the same value used by the kernel). This removes an assertion error in the ramstage. Also change the PMIC driver to assert maximum VSEL values based on the LDO, because the lower-voltage ones support one more setting. (LDO3 is actually listed to only go up to 0b1111 in the manual, and has a weird jump from 0b1101 -> 2.2V (skipping over 0b1110) to 0b1111 -> 2.5V. I don't know if that's a documentation error or what they were smoking when they designed that, but we don't need to care for now.) BRANCH=None BUG=None TEST=Booted on Pinky, no more ASSERTION FAILED. Change-Id: I38bf99e38822fd0883fd4d0bd9a1b01143545a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f3149efbc3aa9a03ab3fd5be99d17d9c5e1c87 Original-Change-Id: I68a3bb882cf25d98aca8922ede2a17e1ef6524de Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228292 Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-on: http://review.coreboot.org/9547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Remove board ID based assumptionsJulius Werner
The veyron_jerry board code was just copied over from veyron_pinky 1-to-1. The Jerry board IDs start at 1, but there has never been a Jerry rev0 so we can remove the code for board ID 0 from it. BRANCH=none BUG=None TEST=Booted Jerry image on a Pinky rev2, worked fine. Change-Id: I0f2ffdc577934c1695e8d2dcf71512696ac1d5a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aa36da69ac584b845e15282dae100eec27fc7f12 Original-Change-Id: I45a18b288c8d8b1399ceedf582addcce1c7e857d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228254 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9546 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change eMMC enable pin to be pulled (not driven) highDoug Anderson
The eMMC enable pin is in a 3.3V IO domain. Unfortunately the eMMC expects this pin to be 1.8V. The way we were driving this pin would cause the eMMC to pull power through this pin and that was causing current leaks. In future revisions of hardware we should move this pin somewhere more legit. However, in the current hardware we can get things working pretty well by using a pullup to "drive" this pin. This will work in conjunction with the external 100K pullup to give a somewhat reasonable voltage. The eMMC will also not be able to pull much current through this pin, so it can't leak too badly. BRANCH=none BUG=chrome-os-partner:33319 TEST=Boot a kernel that doesn't touch the mux/pulls and see no leak: dut-control --port=${SERVO} vcc_flash_ma -t 5 Change-Id: Ibc25cd090d826c8215be24a0b5c11d97b5281700 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e7a9d7e067ed4dd859387ee63bf654ab9dc529 Original-Change-Id: Iadfc1477cd478773cc9d159e3fbc22b66b8f0f78 Original-Signed-off-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226039 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9545 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_jerry boardKatie Roberts-Hoffman
This is essentially a copy of veyron_pinky for now. BUG=chrome-os-partner:33269 TEST=build and boot Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225301 Reviewed-on: http://review.coreboot.org/9544 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: copy WiFi calibration data in the CBMEMVadim Bendebury
Invoke the function which copies WiFi calibration data in a CBMEM table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that the WIFI entry is added to CBMEM when the calibration data is present in the VPD. Change-Id: Icab0a2343e88e1d44575eeb608fdf6588aff255b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 68b96f158633cb3a1f157b5a19da39fa7e78f975 Original-Change-Id: I5fa77da98e37b88da01fb7884e713535fc178006 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9543 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: psci: add cpu_on/off supportJoseph Lo
The CPU on/off functions are the method for the Kernel to support CPU hot-plug function in PSCI. To support this, we still need flow controller support to capture the WFI from the CPU and inform PMC to power gate the CPU core. On the other path, we turn on the CPU by toggling the PMC and use flow controller to let go when the power is steady. BUG=chrome-os-partner:32136 BRANCH=None TEST=built the kernel with PSCI enabled, check both of the CPUs are coming up, test the CPU hot-plug is working on Ryu Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5 Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231267 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: No need of invalidating cache line for secondary CPU stackFurquan Shaikh
With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add support for save/restore registers for CPU startup.Furquan Shaikh
startup.c provides function to enable CPU in any stage to save register data that can be used by secondary CPU (for normal boot) or any CPU (for resume boot). stage_entry.S defines space for saving arm64_startup_data. This can be filled by: 1) Primary CPU before bringing up secondary CPUs so that the secondary can use register values to initialize MMU-related and other required registers to appropriate values. 2) CPU suspend path to ensure that on resume the values which were saved are restored appropriately. stage_entry.S provides a common path for both normal and resume boot to initialize saved registers. For resume path, it is important to set the secondary entry point for startup since x26 needs to be 1 for enabling MMU and cache. This also ensures that we do not fall into false memory cache errors which caused CPU to fail during normal / resume boot. Thus, we can get rid of the stack cache invalidate for secondary CPUs. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu without mmu_enable and stack cache invalidate for CPU1. Change-Id: Ia4ca0e7d35c0738dbbaa926cce4268143c6f9de3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f5e78469313ddd144ad7cf5abc3e07cb712183a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I527a95779cf3fed37392b6605b096f54f8286d64 Original-Reviewed-on: https://chromium-review.googlesource.com/231561 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add macro to invalidate stage 1 TLB entries at current ELFurquan Shaikh
BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Ia4941a864dd3394689121a8c9ddfaaf6f5c150a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e43a081f7394b2014d89e723f816f1eca83ef49 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I60d77456573a2a1e854d9f3ca730237acfb77728 Original-Reviewed-on: https://chromium-review.googlesource.com/231698 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9539 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add conditional read/write from/to EL3 assembly macros.Furquan Shaikh
Some registers are available only at EL3. Add conditional read/write functions that perform operations only if currently we are in EL3. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: Ic95838d10e18f58867b6b77aee937bdacae50597 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62a0e324a00248dba92cb3e2ac2f4072d0e4e2a7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Ia170d94adb9ecc141ff86e4a3041ddbf9045bc89 Original-Reviewed-on: https://chromium-review.googlesource.com/231549 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9538 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
TCR at EL1 is 64-bit whereas at EL2 and EL3 it is 32-bit. Thus, use 64-bit variables to read / write TCR at current EL. raw_read_tcr_elx will handle it automatically by accepting / returning 32-bit / 64-bit values. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I96312e62a67f482f4233c524ea4e22cbbb60941a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae71f87143f899383d8311a4ef908908116340d7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I459914808b69318157113504a3ee7cf6c5f4d8d1 Original-Reviewed-on: https://chromium-review.googlesource.com/231548 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9537 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
Update non-vboot2 memlayout: 1) Add timestamp region 2) Increase ramstage size 3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot upstream board can also use this layout. BUG=None BRANCH=None TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of vboot2. Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f Original-Reviewed-on: https://chromium-review.googlesource.com/231547 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9536 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Change memlayout to have PRERAM and POSTRAM CBFS CacheFurquan Shaikh
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split them into PRERAM and POSTRAM CBFS_CACHE. BUG=None BRANCH=None TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu. Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf Original-Reviewed-on: https://chromium-review.googlesource.com/231546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9535 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Bump up ramstage to 256KFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ia4875948e0be5e084f54f1acb1c5acf5cdabad94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038e9abe2c6e1813cad50bb768e1f66cdd056ccd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If5df6e0dbf85c837f9ada6a967fd3d01b5230307 Original-Reviewed-on: https://chromium-review.googlesource.com/232002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9533 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add speaker amp config for AD4567 on P0/P1Tom Warren
A couple of regs need to be poked to allow audio output from this part on Ryu P0/P1. It will be replaced by two non-configurable amps on P3. BUG=none BRANCH=none TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34) regs and confirmed settings. Change-Id: Ie602b056fb1488546ab233f8f81cfacb96624ebb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75dabe378b561e939381e2ef5113a2b28bfcedf8 Original-Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: prepare cpu startup in psciAaron Durbin
In order to start CPUs while in secmon/psci one needs to set up the proper SoC state. Therefore, refactor the current CPU startup API to allow for this by adding cpu_prepare_startup() and start_cpu_silent(). BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted kernel. Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350 Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231936 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9531 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: psci: actually inform SoC layer of CPU_ON entryAaron Durbin
psci_soc_init() was added to allow SoC PSCI initialization. However, actually calling said function was omitted accidentally. BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and noted correct on entry point was used. Change-Id: I84a397e2dabf149fe8f252ef69d0a7362fa1f194 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a0e6ad41f049bbab483423231db59390894e9b2 Original-Change-Id: I1a4e25fde64ecdc98fa9231f7d9cafc21119630d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231935 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSIJimmy Zhang
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested the default delay of 500us when calling function pmic_write_reg(), it is safe to remove this 100ms delay. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I2cfda38728db223c26f9122b70d37e828921459a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3 Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331 Original-Reviewed-on: https://chromium-review.googlesource.com/231170 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase size of bootblock due to overflowTom Warren
The bootblock on Rush had bumped up into the verstage allocation, causing the build to break. Reduced verstage from 60K to 58K and increased bootblock from 20K to 22K. Rush and Ryu both build fine now. BUG=none BRANCH=none TEST=Built both Rush and Ryu OK. Verifed verstage size using cbfstool and it's around 55K, so plenty of room. Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/230824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: ensure secondary CPU's stack tops are not in the cacheAaron Durbin
Secondary CPUs were intermittently not coming online as expected. Upon investigation it was found that a cache line needed to be invalidated that corresponded to the top of the stack for the failing CPU. Currently the secondary CPUs come online with caching disabled. However, the code paths are using C and thus the stack it is assigned. The MMU is enabled in C after it's pushed its return path onto the stack that went directly to ram. When the cache line corresponding to its stack is valid in the cache it will hit once the MMU is enabled. That hit will have invalid data w.r.t. the return addresses pushed directly into ram. This is not the best solution as the only way to guarantee we don't hit such a situation is to tightly manage resource usage up until the point of MMU enablement. That can be done in a followup patch. BUG=chrome-os-partner:33962 BRANCH=None TEST=On ryu where secondary CPUs weren't coming online consistently, they now come up. Change-Id: I03237656da180d1f74df3a8e00029ba8d778bca8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06ab6afc996cf92c45d4cd6850e31167c2946a95 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: I32de749ea48c19e23442e6dc5678c5369ac3b2b6 Original-Reviewed-on: https://chromium-review.googlesource.com/231219 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9527 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: add timeout waiting for CPUs to come onlineAaron Durbin
The initial MP code assumed all CPUs would come online. That's not very defensive, and it is a bad assumption. Provide a timeout mechanism for bring CPUs online. BUG=chrome-os-partner:33962 BRANCH=None TEST=Multiple times with CPUs working and not working. Boot to kernel. Change-Id: Ib0aef31f5c732816d65c2e4b3c6a89e159974fdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9cf5bc2844c8f4ad987cfcb69ef33c73551f0083 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: Ifb3b72e3f122b79e9def554c037c9b3d6049a151 Original-Reviewed-on: https://chromium-review.googlesource.com/231070 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: always bring up PLLDAaron Durbin
The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: rename clock_display() to clock_configure_plld()Aaron Durbin
Provide an explicit name for configuring PLLD. The new name, clock_configure_plld(), provides an explicit semantic to what it is doing. Also, provide the printk() about actual frequency vs requested frequency as most of the callers were doing this themselves. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted on ryu. Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48 Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.Tom Warren
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz) for MCLK1, I2S1 for input. AHUB needs all of its child peripherals taken out of reset and enabled, too. This just sets up the audio clocks. More work still to be done in the codec driver, and some kind of stub needs to be created/hacked to set up the AD4567 speaker amp regs for mono output on P1. BUG=chrome-os-partner:32582 BRANCH=none TEST=Dumped clock regs and saw correct values Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229993 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9523 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Set dc to resize the difference between framebuffer and panelJimmy Zhang
Scale framebuffer resolution to panel resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Idb19f5871605e878ea380cc8f701a377350681fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2f08a704fe3a7be1e0448e4ed864c69b50d6838 Original-Change-Id: I5ac01539da3712cd6afdb8d08513da399ace0f92 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229494 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add framebuffer resolution settingsJimmy Zhang
When displaying a 800x600 bitmap on 2560x1800 panel, the image is shown very small. So, set the fb to 1280x800 (based on tegra dsi driver default mode setting), a 800x600 image can be shown relatively proportional to panel size. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa Original-Reviewed-on: https://chromium-review.googlesource.com/229912 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9521 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add framebuffer parametersJimmy Zhang
Framebuffer line size and number of lines can have different values than panel's resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229915 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9520 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Expand ramstage size to 208k (from 192k)Jimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Ief81194381193ef9acc7c1786915945d66f2efdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 826ce3730f6d26c9f7a8c3f0429ab14a213172e8 Original-Change-Id: Icc62c776db6f8d8b27615c467518e9753627e72c Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229914 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9518 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add dsi driverJimmy Zhang
Add dsi and related dc, panel configuration functions. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3 Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227202 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add dsi panel mode settingsJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add panel mode specJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I23dae7bfdeb8e33a6ea5c9de0fb953a7c4d31345 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6cac26deeea0e024f2f6bd1850a41894f801bc5f Original-Change-Id: Ie77f8df4ba3425e0dd4e4243dd38157480de0efb Original-Reviewed-on: https://chromium-review.googlesource.com/229913 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9515 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: dsi: Enable panel related vdd and clocksJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ia10bf7ae3bde389e883970f9a6ee931c32b8172b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26902364b6a453adb850abfb0c4ce9686e99b5d Original-Change-Id: I68b92608098959cca14324bfc7e1e58389205989 Original-Reviewed-on: https://chromium-review.googlesource.com/226905 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Disable EC SW sync for proto boards before proto3Furquan Shaikh
BUG=chrome-os-partner:33583 BRANCH=None TEST=No EC SW sync messages seen in depthcharge boot flow. Change-Id: I62b7061a833ba607457a580fb2b217b9c2df0e74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 552b1d19bacd6692ffb6257fc81220ba0ed89344 Original-Change-Id: I5c1df5a23977f461011a2937adda5770b4742378 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229081 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase space for romstage in memlayoutFurquan Shaikh
Stack and Timestamp need lesser than 2K and since romstage is running out of memory, adjust the overall memory assignment. BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I5076252ae87268bd4e964c282d1cc337e0ea4e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2d5d29e6f0f5058a41ed30aae98f79574e31609 Original-Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9512 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10urara: support building with CHROMEOS enabledVadim Bendebury
Chrome OS support needs to be enabled on urara. This patch adds a placeholder file to keep Chrome OS support code. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I0731469934f04bd68914f09db5d64758c5d01545 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 169c62c9443c3b9fcab23b312b5cb18ba79437f4 Original-Change-Id: I8ec328d4f965ff80d17847f2f8ce62b402c42a46 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226179 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
According to BYT platform design guide chap 14.2.2, the NC GPIOs need to be configured to GPO. BRANCH=none BUG=none TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591 Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/249060 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
Log the new EC panic host event. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7 Original-Reviewed-on: https://chromium-review.googlesource.com/252391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: http://review.coreboot.org/9508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10cros_ec: Retry failed VBNV transactionsJulius Werner
This patch adds a few retries to NVRAM read/write transactions with the EC. Failing to read the NVRAM is not fatal to the boot, but it's still pretty bad... especially since a single initial read failure will cause vboot to blindly reinitialize the whole NVRAM with zeroes, destroying important configuration bits like dev_boot_usb. The current EC transaction timeout is one second, so the three retries added here can potentially increase boot time by three seconds per transaction... but this shouldn't happen in any normal case anyway, and if there are errors a little extra wait is probably preferrable to nuking your NVRAM. (Also, added a missing newline to an error message in the EC code.) BRANCH=veyron BUG=chrome-os-partner:36924 TEST=Booted a Jerry with the power button bug with a 2 second press, noticed that the first two transactions failed but the third one succeeded. Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251694 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Enable vr_slow_rampShawn Nematbakhsh
Enable slow ramp rate to reduce idle noise / crackle. BUG=None TEST=Performance/noise/power tested by others. BRANCH=Samus Change-Id: I3b0083bdb19f96fc018356bd744fdff3baaf8962 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 041fca21b863d3fd94dd5bebf89fe48f5ac74285 Original-Change-Id: Id7e55f3710304369a79150129db18300ae38f93a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248791 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10x86: Support reset routines in bootblockLee Leahy
Expand the boot block include file to allow for a file containing reset routines to be added. Prevent breaking existing platforms by using a Kconfig value to specify the path to this file, and have the code include this file only if the Kconfig value is set. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51 Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9504 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
Looks like Intel has added two more USB 2.0 ports from LynxPoint to Broadwell, which shifted the port offsets of the USB 3.0 ports behind them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to 0x560 (at least according to what my kernel seems to think). The offset of the first USB 3.0 port is hardcoded and seems to have been copied over without accounting for this, meaning when we try to operate on all USB 3.0 ports we actually operate on the last two 2.0 and the first two 3.0 ports instead. This patch should fix the bug for now. In the future, we might want to consider dynamically detecting port locations through the Protocol Capability structures at the end of the XHCI register set instead. BRANCH=samus BUG=chrome-os-partner:35320 TEST=TODO Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397 Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247351 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-on: http://review.coreboot.org/9502 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors. BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9501 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
This is needed for audio playback after we disconnect PP1800_CODEC from DACREF to avoid noise coupled on PP1800_CODEC, which makes recording noisy. For recording, DACREF comes from mic vref pump voltage. For playback, DACREF comes from internal 1.8V. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241179 Reviewed-on: http://review.coreboot.org/9500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:53:00 +0000