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2018-05-07mb/sunw: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I348a7ad368cf5b5a7837c45038a1659a581c518f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2018-05-07lib/bootmem: ensure ramstage memory isn't given to OSAaron Durbin
When RELOCATABLE_RAMSTAGE is employed ramstage lives within the cbmem area. Don't mark it as OS usable under that circumstance. Change-Id: Ie15775806632bd943b8217c433bc13708904c696 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-06AGESA: Remove remains of HT recoveryKyösti Mälkki
While built, this code was never called. Change-Id: Ie8216d8f4636330d38ea02aab83bc9e440864f17 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA f14: Remove early HT initKyösti Mälkki
Syncronise HT init code with f12 vendorcode. Constructor for HT init is not required since init itself is not called. Change-Id: I0552c4d019c700f84d98473978afb18fe4eea1e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Run ar with DTKyösti Mälkki
Create libagesa as a thin and deterministic archive file, this could reduce build time and used space. Change-Id: Icfd1f3fbf54f7e61ab528fa7686331182959c7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/22068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-05util/release/genrelnotes: Add "sifive" search patternJonathan Neuschäfer
Make sure that SiFive-related code is counted under RISC-V in the release notes. Change-Id: I3a74bb25ea66c98bc194adafd8267afeb42d7993 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25987 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-05intel/acpi: Fix ACPI compile errorLijian Zhao
According to ACPI 6.1 spec 19.6.44, External informs compiler that object is external to this TABLE, no necessary for object in same DSDT tables. BUG=None TEST=Build pass Intel mainboard with 20180427 iasl. Change-Id: I153e7d0e97f9a29919676fbb73a7c26fd22f252c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-05soc/intel/cannonlake: Include stage cache support for CNLSubrata Banik
TEST=Build and boot cannonlake rvp. cpu_index() returns correct cpu index based on caller. Change-Id: I23f80ef455d075a14121577f401cfc7c44ba0cfa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-05soc/intel: Add KBL-R pci id supportLijian Zhao
Add KBL-R internal graphics device pci ids into coreboot. BUG=N/A TEST=Boot up fine on kabylake-r platform with display on. Change-Id: I0813247624770b70fe8b3ec3825fd17a9878cd0e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
2018-05-05mainboard/ocp/wedge100s: Initial commitDavid Hendricks
This patch does the following: 1. Copy src/mainboard/intel/camelbackmountain_fsp to src/mainboard/ocp/wedge100s. 2. Update Kconfig files 3. Add board.fmd 4. Enable VPD The OCP Wedge100S is a 100GbE top-of-rack switch with a Xeon D-1500 com-express module. More info is available at http://www.opencompute.org/wiki/Networking/SpecsAndDesigns. Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: Ia150b066124953c7c0abe8ea5a13e4131194ea00 Reviewed-on: https://review.coreboot.org/25671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-05fsp_broadwell_de: Add option to enable EHCI controllersDavid Hendricks
Change-Id: I74ee9448923015ac5ec3eec770669f3491a375ba Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-05mainboard/ocp/monolake: Initial commitDavid Hendricks
This patch does the following: 1. Copies mainboard/intel/camelback_fsp to mainboard/ocp/monolake 2. Adds Kconfig files to mainboard/ocp 3. Makes minor board-specific changes (board_info.txt, Kconfig variables) The OCP Mono Lake platform consists of up to 4 single-socket Xeon D-1500 microservers in a Yosemite v1 chassis. More info is available at http://www.opencompute.org/wiki/Server/SpecsAndDesigns. Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: If358162abe67e9411fd2514d48f3b3411da15f68 Reviewed-on: https://review.coreboot.org/25669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-04soc/intel/common: Allow exporting the size of the VBTPatrick Georgi
Change-Id: Ib340aad846ea7cb61d650928b495efaa1fc2d641 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-04soc/intel: unify VBT fetching APIPatrick Georgi
Skylake used the inner function, wrapping it in the same set of tests as the common code does, but expressed differently. Change-Id: Ifa6912255e7874a6e80301d49128adda6f624209 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26037 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04cpu/x86/mp: use __aligned macroAaron Durbin
Now that __aligned is around, take advantage of it. Change-Id: I93cdbe108d752088f34d3f5722dce5d9b90bcdc3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26022 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04cpu/x86/mp: remove unused functions and limit API exposureAaron Durbin
barrier_wait_timeout() was not used anywhere in the code. The remaining two functions, barrier_wait() and release_barrier(), are not used anywhere but the mp code. Change-Id: If09991f95306becc68b6008ae6448695fb4a2dca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26021 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04amd/mct/ddr3: Correctly configure CsMux67Patrick Georgi
The existing logic to set up CsMux67 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Commit cf1cb5b2d4f528e7eab55ee9393cf72016bac888 did the same for CsMux45 but missed this one. Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25994 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELFPatrick Rudolph
In preparation of having FIT payloads, which aren't converted to simple ELF, rename the CBFS type payload to actually show the format the payload is encoded in. Another type CBFS_TYPE_FIT will be added to have two different payload formats. For now this is only a cosmetic change. Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04superio/ite/common: Add options to enable beepsVagiz Trakhanov
Add device tree options to enable beeps when exceeding temperature, voltage, and fan limits. As of this commit, setting voltage and fan limits is not implemented. Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/ricoh/rce822: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/uart/oxpcie.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/drivers/lenovo/wacom.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/i210.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/gma/opregion.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/root_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pci_class.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pcix_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/smbus_ops.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/cardbus_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pciexp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pnp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04console/vtxprintf.c: Add required spaces around '>'Elyes HAOUAS
Change-Id: I2e1e494f40bf2316e02a96759a92c933ee11fbab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04arch/x86/cpu.c: Remove unneeded headersElyes HAOUAS
Change-Id: I35fcf25906bf7fe5af133618654bb121404743fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04arch/x86/cpu_common.c: Remove unneeded headersElyes HAOUAS
Change-Id: I4f57376138725804133059c785e89e095fd6a759 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04lib/bootmem: Add method to walk OS POV memory tablesPatrick Rudolph
Add method to walk memory tables from OS point of view. The tables don't change when modifiying bootmem entries and doesn't contain bootmem specific tags. Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add method to walk memory tablesPatrick Rudolph
Add a method to walk bootmem memory tables and call a function for each memory range. The tables might not match with OS sight of view. Return true if the callback function returned false. Required for FIT support in coreboot to find a usable RAM region. Tested on Cavium SoC. Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add more bootmem tagsPatrick Rudolph
Introduce new bootmem tags to allow more fine grained control over buffer allocation on various platforms. The new tags are: BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that should not be touched by bootmem (by example: stack, TTB, program, ...). BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should not be touched by bootmem. Starting with this commit all bootmem methods will no longer see memory that is used by coreboot as usable RAM. Bootmem changes: * Introduce a weak function to add platform specific memranges. * Mark memory allocated by bootmem as BM_TAG_PAYLOAD. * Assert on failures. * Add _stack and _program as BM_MEM_RAMSTAGE. ARMv7 and ARMv8 specific changes: * Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE. ARMv7 specific changes: * Add _ttb_subtables as BM_MEM_RAMSTAGE. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04mainboard/hp/dl145_g1: Remove commented codeElyes HAOUAS
Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04mainboard/google/kahlee: Pass oscout system clk to da7219Akshu Agrawal
Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04drivers/i2c/da7219: Add mclk-name propertyAkshu Agrawal
Non-dts based systems can pass mclk to da7219 driver by this property. BUG=b:74570989 TEST=Enabled clock in kernel driver using the property Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04soc/amd/stonyridge: Add misc deviceAkshu Agrawal
oscout system clock is present in FCH misc device. The kernel acpi misc driver will use the resource to register oscout system clock. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04ifdtool: Add a list of known platforms that support IFD_VERSION_2Furquan Shaikh
ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. However, newer platforms like GLK and CNL do not have read_freq field in FCBA and so the value of these bits cannot be used as an indicator to distinguish IFD versions. In the long run, we need to re-write ifdtool to have a better mapping of SoC to IFD fields. But until that is done, this change adds a list of platforms that we know do not support read_freq field but still use IFD_VERSION_2. This change also updates GLK and CNL to pass in platform parameter to ifdtool. BUG=b:79109029, b:69270831 Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04commonlib: Add descriptions for new AGESA timestampsMartin Roth
When the latest AGESA timestamp values were added, the descriptions weren't added along with them. Because of this, the cbmem tool just shows them as "<unknown>". Bug=b:79153552 TEST=None Change-Id: Iad7bcd53bc6136b74d4d933d1a290feac6a0de56 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26001 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04google/kahlee: Revert "Resume on AC insertion"Martin Roth
This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04soc/amd/stoneyridge: Remove USB30PortInit settingMartin Roth
This bitmask sets the USB PORTSC.DR bit for each XHCI port. This is mainboard specific, and only for non-removable devices attached to the XHCI port. BUG=b:72859972 TEST=Boot grunt Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationKyösti Mälkki
Fix (assumed) regression with commit ac63b41 vendorcode/amd/agesa: Fix variable length array declaration The code used sizeof() on the struct where array length was previously adjusted, but only f14 case was fixed accordingly. Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26036 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03pci: Add dummy file for ARM64Patrick Rudolph
Add stub files to support compiling the PCI driver on ARCH_ARM64. Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-03pci: Fix function prototypePatrick Rudolph
Fix a function prototype to support PCI on non x86. The function itself does have the correct argument already. Change-Id: I564fcfe9b85ed4f841a48fe17a3f5bf80e16560b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 16:00:14 +0000