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2019-10-21soc/mediatek/mt8183: Force DRAM retraining if hotkey pressedYu-Ping Wu
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21soc/mediatek/mt8183: Skip fast calibration in recovery modeYu-Ping Wu
SoC DRAM team suggested always running full calibration mode in recovery mode because it is possible to get unstable memory even if the complex memory test has been passed. Since the recovery mode runs from RO and we only have training data cache for RW, the trained calibration data can't be saved since RO and RW may be running different firmware. Also revised few message to make it more clear for what calibration mode (fast, full, or partial) has been executed. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21mb/google/hatch/var/dratini: Add ELAN touchscreen supportWisley Chen
Add ELAN EKTH6915 USI touchsreen support. BUG=b:139392144 TEST=check touchscreen work, and confirmed power sequence with vendor. Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21Revert "soc/intel/cannonlake: Remove DMA support for PTT"Jeremy Soller
This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c. Reason for revert: Breaks boot on Whiskey Lake-U boards Both System76 and Purism have had memory initialization failures when this patch is applied, with the following error message: Failed to accommodate FSP reserved memory request! An extra 4096 bytes needs to be reserved for the FSP on these systems, and reinstating the PTT reservation does this as expected. PTT is enabled for the System76 galp3-c in the ME configuration, which is why the behaviour is different. Signed-off-by: Jeremy Soller <jeremy@system76.com> CC: Matt DeVillier <matt.devillier@gmail.com> CC: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sc7180: Provide initial SoC supportT Michael Turney
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-21google/poppy: add VBT for nautilus variantMatt DeVillier
Add data.vbt and modify Kconfig appropriately; allows use of FSP/GOP display init. VBT extracted from stock ChromeOS firmware. Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-21purism/librem_bdw: hook up libgfxinitMatt DeVillier
Test: build/boot Librem 13v1, 15v2 with libgfxinit Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36108 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sb/lynxpoint: Fix 'dead increment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Change-Id: I631524b9346647048fe8ea30387553a5b4651f59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21mb/google/hatch/akemi: disable unused devices for AkemiPeichao Wang
Akemi unused devices declare: - I2C #1 gpio_keys - close I2C #3 - close GSPO #1 BUG=b:142800988 TEST=Reboot stress test and suspend stress test, the DUT will be able to working properly Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086 Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/facebook/fbg1701: rename mainboard.h to logo.hWim Vervoorn
Renamed mainboard.h to logo.h as it only contains logo related items. BUG=N/A TEST=tested on fbg1701 Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-20soc/amd/picasso: Increase max APCB images to 5Marshall Dawson
An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20util/amdfwtool: Add holding locations for more APCBsMarshall Dawson
Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20drivers/intel/fsp2_0: Make vbt_get() conditionalMarshall Dawson
Skip calling vbt_get() if FSP is not supposed to run GOP. Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiBV Sowmya
The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since the default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Correct a few GPIO namesMarshall Dawson
Fix a handful of errors that slipped through in 2e0f2788 "soc/amd/picasso: Update GPIO configuration". Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36118 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src/soc/amd/common: Add Azalia support to HDAMarshall Dawson
Let the mainboard decide whether to let coreboot load the verb table. Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35274 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20pci_ids: Add AMD Family 17h ACPMarshall Dawson
Add Picasso's Audio Coprocessor Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36116 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Add cpuid for older deviceMarshall Dawson
Make the driver work with stepping=0. Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35273 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20vc/amd/fsp: Add UPD header files for picassoMarshall Dawson
Add files for Picasso's FSP UPD definitions. These are automatically generated from the FSP build. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20cbmem: Add IDs for TSEG and BERT table dataMarshall Dawson
Prepare for products that can use any DRAM for TSEG. Include an ID for data pointed to by an ACPI BERT table. This region's only requirement is it is marked reserved. Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36115 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Adjust I2C ASLMarshall Dawson
Clarify names as I2C2, etc. Use iomap.h defines for base addresses. Update IRQs. Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update iomapMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33991 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Update UARTsMarshall Dawson
Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Add display identification and vbios nameMarshall Dawson
Add Picasso's Device ID and default filename. Only a single Device ID is documented for Picasso so remove the oprom remapper function. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34422 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Remove unused SATA configurationsMarshall Dawson
Picasso's SATA controller operates only in AHCI mode. Remove the Kconfig symbols previously used to select between other possibilities. Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Remove SATA from AOAC registersMarshall Dawson
SATA is no longer defined in AOAC so remove its definitions. Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update southbridgeMarshall Dawson
Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/common: Add AcpiMmio access for SMBus PCI deviceMarshall Dawson
The standard PCI register space for D14F0 is accessible at 0xfed80000. Add functions for use as helpers. Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/common/lpc: Add SuperIO decode functionMarshall Dawson
The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Update for USB3.1Marshall Dawson
Change to the appropriate device IDs. Remove the ehci resource call. Remove overcurrent settings, as this will be passed to AGESA in later change. Remove unused USB2 ACPI name assignment. Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update all PSP and amdfw.rom buildingMarshall Dawson
Add Kconfig options and Makefile command line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are not public information. See NDA document PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20superio: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20superio: Remove unused include <device/smbus.h>Elyes HAOUAS
Change-Id: Ic8a28493c386c0097dbf3478e6d046fdfbf28724 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20security/memory: Add x86_64 supportPatrick Rudolph
Fix compiler warning by adding an additional check for the fastpath memset. Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20mb/lenovo/x200: Add ThinkPad X301 as a variantBill XIE
It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-19mb/lenovo/x201/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36128 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-19mb/lenovo/x200/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-19util/ifdtool: Add support for setting flash density on IFD V2Arthur Heymans
Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-18mb/google/octopus: Create Dood variantTim Chen
This commit creates a dood variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:141960652 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-18src: Remove unused include '<device/pci_ids.h>'Elyes HAOUAS
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18build: Mark bootblock files on x86 as IBBPatrick Rudolph
* Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/intel/common: lpc/espi: fix wrong lock bitMichael Niewöhner
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-18superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.aslPavel Sayekat
This port is based on NCT6776 Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory supportFrans Hendriks
FBG-1701 revision 1.3 will use Kingston onboard memory. Add Kingston SPD file. When Samsung memory configuration is disabled use cpld_read_pcb_version() for using correct SPD data. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 revision 1.3 Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792 Reviewed-by: Wim Vervoorn Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18superio/smsc: Restore sio1036Marshall Dawson
Change d3a1a417 "src/superio: Remove unused superio chips" removed all unused devices except for ones used on mainboards still under review. The SMSC 1036 was inadvertenly also removed as well. This device is used in debug cards that may be connected to AMD CRBs. This patch restores the smsc1036 directory as-is and then corrects the following lint messages. * WARNING: Prefer 'unsigned int' to bare use of 'unsigned' * ERROR: else should follow close brace '}' * WARNING: braces {} are not necessary for single statement blocks Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: separate cpld supportWim Vervoorn
Move all code involving the cpld to a single file. Rename mainboard_read_pcb_version() to cpld_read_pcb_version(). BUG=N/A TEST=tested on fbg1701 board Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
The change applies the DPTF parameters. BUG=b:142849037 TEST=build and verified by thermal team Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-18soc/mediatek/mt8183: Compress calibration blob with LZ4Hung-Te Lin
The DRAM calibration blob can be compressed using pre-RAM algorithm (currently LZ4), which will save ~12ms in boot time. On Kodama, boot time difference: Before: 1,082,711 After: 1,070,309 BUG=b:139099592,b:117953502 TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed) BRANCH=kukui Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 11:37:03 +0000