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2019-03-07soc/intel/cannonlake: Move power_state functions to pmutil.cV Sowmya
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. BUG=b:124131938 BRANCH=none TEST=none Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-07src/device/Kconfig: Include the discrete VGA OpROM at config UIMike Banon
Create the way of adding the discrete VGA OpROM at config UI (alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_VGA_BIOS is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-07intelmetool: Add more flag descriptionsDamien Zammit
Obtained by inspecting intel SPSinfo tool output Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e Author: roncapat Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31589 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07intelmetool: Consolidate all model support from upstreamDamien Zammit
Some of the older chipsets that are known not to have ME at all were removed for some reason, add them back in. Also some newer chipsets/ME models were missing, add them in. Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-07prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if existSubrata Banik
This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=It's been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on Intel platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07arch/x86/postcar: Add separate timestamp for postcar stageSubrata Banik
This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07soc/intel/icelake: Add PM timer emulation support in ICLAamir Bohra
CPU PM TIMER EMULATION logic will help UEFI payload to execute rather wait for time tick in absence of TCO and ACPI PM timer after FSP-S. BUG=N/A TEST=Able to build and boot with tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-07mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.hElyes HAOUAS
Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07vboot: rename VB2_DISABLE_DEVELOPER_MODEJoel Kitching
Rename VB2_DISABLE_DEVELOPER_MODE to VB2_CONTEXT_DISABLE_DEVELOPER_MODE. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460645 BRANCH=none Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-07vboot: rename VB2_SD_DEV_MODE_ENABLEDJoel Kitching
Rename VB2_SD_DEV_MODE_ENABLED to VB2_SD_FLAG_DEV_MODE_ENABLED. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460644 BRANCH=none Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-073rdparty/blobs: Update submodule pointerNico Huber
* Update SMU firmware for amd/stoneyridge * Remove stale Sandy Bridge MRC binaries Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07Docs/project_ideas: Add coverity scan cleanup projectPatrick Georgi
Change-Id: I16d9a7f7088254c5c207adc9299a8525bf38199f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-07Documentation: Add myself as potential mentor for QEMU targetsPatrick Georgi
Change-Id: I11df0283f14ae03243247fe9377754b216df0442 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07Add new CONFIG(XXX) macro to replace IS_ENABLED(CONFIG_XXX)Julius Werner
The IS_ENABLED() macro is pretty long and unwieldy for something so widely used, and often forces line breaks just for checking two Kconfigs in a row. Let's replace it with something that takes up less space to make our code more readable. From now on, if (IS_ENABLED(CONFIG_XXX)) #if IS_ENABLED(CONFIG_XXX) shall become if (CONFIG(XXX)) #if CONFIG(XXX) Change-Id: I2468427b569b974303084574125a9e1d9f6db596 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07mainboard/google/kahlee: Add additional Micron MT40A512M16TB-062E:J SPD for ↵Kevin Chiu
variants BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Remove fanless SMU optionsMarshall Dawson
Complete the removal of the fanless command line options. The only soc using them has been converted to use the subprogram option instead. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07soc/amd/stoneyridge: Convert SMU fanless optionsMarshall Dawson
Change the amdfwtool command line arguments to use the new --subprogram option. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: Iaae4094251974b8dad48b8d2c37bb2e43a412237 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31736 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Split type field for PSP entriesMarshall Dawson
Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Streamline functions with contextMarshall Dawson
Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Add generic image copy functionMarshall Dawson
Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Combine table header populationMarshall Dawson
Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Remove duplicate PSP2 supportMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07soc/amd/stoneyridge: Call amdfwtool with different argumentsMarshall Dawson
To prepare for consolidating amdfwtool command-line options, change the stoneyridge makefile to use the ones that will be kept. By using the new --combo-capable option, the PSP directory's pointer still appears in the correct location within the the Embedded Firmware structure. TEST=Confirm amdfw.rom file is unchanged before/after when building google/grunt BUG=b:126691068 Change-Id: Ia31ebdcb8c392d75c56811b60f1ae673f7ba79cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31730 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Introduce combo-capable optionMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 1 of 2 to reduce the number of command-line options to amdfwtool. Create a new option that is used as an indicator for which Embedded Firmware offset to use. Part 2 will be added once makefiles no longer use the duplicated options. This patch also adds two new options for fanless SMU firmware to be used instead of the ones that will be removed in part 2. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied BUG=b:126691068 Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Clarify call to fletcher32Marshall Dawson
The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Clarify calculations with structuresMarshall Dawson
Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Fix iteration of PSP firmwaresMarshall Dawson
Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06soc/intel/skylake: Add H110 PCH seriesMaxim Polyakov
This patch adds support H110 chipset (Sunrise Point) for Skylake and Kaby Lake processor families by adding the corresponding IDs. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06soc/intel/skylake: Add new Northbridge and IGD IDsMaxim Polyakov
This patch adds support 1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host Bridge/DRAM Registers - 191F; 2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor https://en.wikichip.org/wiki/intel/hd_graphics/530. This is required to run coreboot on the Intel Core i5-6600 (Skylake) desktop processor. It has been tested on ASRock H110M-DVS motherboard. Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06soc/intel/braswell/include/soc/spi.h: Add OPTYPE valuesFrans Hendriks
Add SPI_OPTYPE_XXX values for the SPI controller. BUG=N/A TEST=flashrom on Facebook FBG-1701 Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-03-06MAINTAINERS: Update Braswell SoC maintainersMichał Żygowski
Remove former Intel employee from maintainers of Braswell SoC. Add 3mdeb and Eltan representatives as Braswell SoC maintainers. Also mark Braswell SoC as maintained. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id815db60e3718bf141abcc7923ea073bbab4a516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2019-03-06soc/intel/braswell/include/soc/pci_devs.h: Add PUNIT_DEVFrans Hendriks
Intel Braswell P-UNIT is missing in pci_devs.h Add PUNIT device, function and device ID BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31711 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06mb/google/poppy/variants/nami: Use Pantheon VBTJohn Su
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06mb/google/sarien: add ish firmware_variant field to _DSDJett Rink
We want to publish "arcada_ish.bin" as the fw name for Integrated Sensor Hub (ISH) so the kernel shim loader code can use it to construct the correct path in /lib/firmware/intel for the firmware load process. BUG=b:122722008 TEST=Verify that shim loader CLs use new value when constructing firmware path Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-06driver/intel/ish: add ish chip driver supportJett Rink
We want to be able to specify the firmware variant suffix in the devicetree.cb configuration for particular firmware builds. This driver allows us to specify the firmware_variant property in the device tree and have it populate a _DST table in the SSDT ACPI table for the ISH device, thus making the suffix available to the kernel (See crrev.com/c/1433482 for kernel change that uses the value) BUG=b:122722008 TEST=decompile DDST table and verify that new firmware-variant value is present. Also verfied that kernel can access this new field using the shim loader kernel CLs Change-Id: Id8be986185282521aee574027503eaf8968e1508 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-06arch/x86: Prepare GDT for x86_64Patrick Rudolph
Make GDT a separate table and don't reuse GDT descriptor as unused first field of GDT. Required for separate x86_64 GDT descriptor, pointing to the same GDT. Tested on qemu. Change-Id: I513329b67d49ade1055bc07cf7b93ff2e0131e0b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31769 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06pci_drivers/cpu_drivers: Fix constructed arrays on x86_64Patrick Rudolph
The __pci_driver and __cpu_driver uses variable length arrays which are constructed by the linker at build-time. The linker always place the structs at 16-byte boundary, as per "System V ABI". That's not a problem on x86, as the struct is exactly 16 Bytes in size. On other platforms, like x86_64 it breaks, because the default data alignment isn't SysV compatible. Set -malign-data=abi to make x86_64 gcc use the SysV psABI. Fixes broken __pci_driver and __cpu_driver on x86_64. Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeSubrata Banik
Update header files for FSP for cometlake platform version 1065 Change-Id: I7be7535975b442490cc77c9c1dca4ef7a2d43a58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-03-06ec/lenovo/h8: Implement ACPI methods to set battery thresholdsAlexey Kharlamov
There are two known reverse-engineered ways to manage battery thresholds. This patch implements them and adds a way to enable them for different mainboards. Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11. Works fine with new Linux userspace API for controlling battery thresholds, available since 4.17. (/sys/class/power_supply/BAT0/charge_(start|stop)_threshold). The new API is supported by TLP (you might need to set NATACPI_ENABLE=1 in /etc/tlp.conf). tpacpi-bat works fine too. Signed-off-by: Alexey Kharlamov <der@2-47.ru> Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINITKyösti Mälkki
Fail builds if MRC blobs pool heap would get corrupted by CAR relocatable data from coreboot proper. Add runtime logging how much pool was required. Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31150 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"Elyes HAOUAS
Change-Id: I58ecd95a8427eba87611dd8ea4616aedbb1d01c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-06device/pci_ops: Inline PCI config accessors for ramstageKyösti Mälkki
Inlining here allows the check for (dev != NULL) to be optimised and evaluated just once inside the calling function body. Change-Id: I0b5b4f4adb8eaa483a31353324da19917db85f4a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-06device/pci_ops: Change ramstage PCI accessor signaturesKyösti Mälkki
This reduces parameter passing and visibility of parsing struct *dev to PCI bus:dev.fn. Change-Id: Ie4232ca1db9cffdf21ed133143acfb7517577736 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-06device/pci_ops: Simplify logic for PCI bus opsKyösti Mälkki
Nobody ever sets ops_pci_bus. This implies pci_bus_ops() always returns pci_bus_default_ops() and get_pbus returns NULL. Change-Id: Ia30d579e1efe6542dc58714f2e7077507847c0de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31684 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06soc/intel: Use simple PCI config accessKyösti Mälkki
Call the simple PCI config accessors directly. Change-Id: I2c6712d836924b01c33a8435292be1ac2e530472 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 03:50:15 +0000