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2014-08-14lenovo/x200: Fix black screen on quick boot.Vladimir Serbinenko
Otherwise without USB when coreboot boots too quickly EC is confused and thinks that LID is closed and so powers off the backlight until user flaps the lid. Change-Id: I14dfaa62582de83fd4c9f9518e9436b3a3035366 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6651 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-08-14gm45: Set D0F0_SKPD on normal boot pathVladimir Serbinenko
Otherwise we get a warning on normal boot. Change-Id: Ida1e1d23e258438251d4ec2417f93ad14c3b9f7d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6652 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-14gm45: Set acpi_slp_type only once.Vladimir Serbinenko
It doesn't harm to set several times but it pollutes the log. Change-Id: I7aad7f0229a7d9d071ba844a1cfa123dffc4cacf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6653 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-08-14libpayload: usbmsc: Split transfers into 64KB chunksDuncan Laurie
Add a new function to split transfer requests into chunks of 64KB in order to be as compatible as possible with devices that choke when sent large transfer requests. Change-Id: Id11990bd149af14af5535de4af47bda21d1ab51e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169170 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 4c413b007aa23da830877127dd556c4c38b43042) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6636 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14ARMv7/Exynos: Fix memory location assumptionsStefan Reinauer
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14exynos5: Refactor crazy old U-Boot base address macros awayJulius Werner
All this samsung_get_base_address_of_device_with_a_really_long_name() boilerplate makes my eyes bleed... I think there are so much cleaner ways to do this. Unfortunately changing this ends up touching nearly every Exynos5 file, but I hope you agree that it's worth it (and the sooner we get it over with, the better... I can't bring myself to make another device fit into that ugly scheme). This also removes the redundant EXYNOS5 base address definitions from the 5420 directory when there are EXYNOS5420 ones, to avoid complete confusion. The new scheme tries to use EXYNOS5 for base addresses and exynos5 for types that are common between the two processors, and EXYNOS5420/exynos5420 for things that have changes (although I probably didn't catch all differences). Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167579 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13exynos5420: Enable relocatable module supportStefan Reinauer
Since we're now supporting ARMv7 relocations, we can enable rmodule support on Exynos 5420. This does not automatically enable relocatable ramstage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic3af1eabb3b816944587a46409224f778d941b8a Reviewed-on: https://chromium-review.googlesource.com/167403 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7b5afef4ee87fc3245ec887dfda873c529d8d04d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6629 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13Tegra,Tegra124: proposed layout for file hierarchy with exampleRonald G. Minnich
This change shows the source structure for nvidia Tegra and Tegra124 SOC. The problem we are trying to solve is that there is a large amount of common code in the form of .c and .h files across many different Tegra SOCs. The solution is to provide common code in a single directory, but not to compile in the common code directory; rather, we compile in a directory for a given SOC. Different SOCs will sometimes need different bits of code from the common directory. Tegra common code lives in tegra/, but there is no makefile there: if a Tegra common file is needed in a SOC, it is referenced via a Makefile in a specific Tegra SOC. Another issue is includes. Include files in the common directory might be accessed by a piece of code in an SOC directory. More problematically, code in the common directory might require a file in an SOC directory. We don't want to put the SOC name in an #include path, e.g. in a C file in tegra/ is very undesirable, since we might be compiling for a tegra114. On some systems this is solved by a pre-pass which creates a set of symbolic links; on others with nested #ifdef in the common code which include different .h files depending on CPP variables. In previous years, both LinuxBIOS and coreboot have tried these solutions and found them inconvenient and error-prone. We choose to solve it by requiring explicit naming of part of the path of files that are in the common directory. This requirement, coupled with two -I directives in the Makefile.inc, allows common and SOC C code to incorporate both common and SOC .h files. .c and .h files -- SOC or common -- name include files in the common directory with the prefix tegra/, e.g. SOC files will be included from the SOC directory if they have no prefix: The full patch of clock.h will depend on what SOC is being compiled, which is desirable. In this way, a common file can pick up a specific SOC file without creating symlinks or other such tricky magic. We show this usage with one file, soc/nvidia/tega124/clock.c. This compiles. The last question is where to put the prototype for the function defined in this file -- soc.h? Change-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/171569 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 53e3bed868953f3da588ec90661d316a6482e27e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6621 Tested-by: build bot (Jenkins)
2014-08-13Falco: Patch to setup FUI (coreboot initializations) for falcoFurquan Shaikh
For now using the same gma.c and i915io.c files as for slippy Change-Id: Ieb09d0152d525aa090eeb86ebfa253d450d22820 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64373 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 3e119c7e22cb82677754413e56a125f4a372ad54) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-13Falco: Patch to enable correct port clock selection for dpFurquan Shaikh
This is required only for haswell since the register configs have changed. Also, created mainboard specific header file Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945 Signed-off-by: Furquan Shaikh <furquan@google.com> Conflicts: src/mainboard/google/slippy/gma.c src/mainboard/google/slippy/i915io.c Conflicts: src/mainboard/google/slippy/gma.c Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5 Reviewed-on: https://gerrit.chromium.org/gerrit/66853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6602 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-13Falco/Slippy: Patch to refactor haswell/gma.c and ↵Furquan Shaikh
mainboard/google/slippy/i915io.c A large portion of documented registers have been initialized using macros. Only a few undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant calls. However, some more work is required to correctly identify which calls are not required. All the io_writes are replaced by gtt_writes. Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66204 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6600 Tested-by: build bot (Jenkins)
2014-08-13lenovo/x200: New mainboard.Vladimir Serbinenko
Change-Id: I64e59648064d5875907b5057e2f9f72f2c5997b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6631 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13lenovo/h8: Support uwb radio.Vladimir Serbinenko
It's the third minipcie slot in x200. Change-Id: Ibfa8d787698cd23b4abcffe5cff2d62039cf0f86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6641 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13gm45: Allow skiping voltage config.Vladimir Serbinenko
Change-Id: I81b9966212d09d4d2561b3adc20d6d8a8a200f4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6630 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13ARMv7: drop dead code from Makefile.incStefan Reinauer
This commented out code is a left over from x86. Change-Id: Ice806000c73d5a068962914d067d4de7b3d75f45 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168961 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 9d700cf35d2283a088e704c0ebd34e6f58f54993) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6639 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-13util/inteltool: Typo in dump output for 'GP_IO_SEL3'Edward O'Callaghan
The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header is incorrectly reported as 'GPIO_SEL3'. Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6459 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13southbridge/amd/cimx/sb800: Uninitialized variables in config funcEdward O'Callaghan
Both 'SbSpiSpeedSupport' and 'UsbRxMode' are uninitiated upon return from a 'sb800_cimx_config()' call. Change-Id: I32237ff97fafc3e69627d427e54268dcb039e12c Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-13chromeos: On ARM platforms VBNV lives in the ECStefan Reinauer
This patch renames the x86 way of doing things to explicitly mention CMOS (which is not available on our ARM platforms) and adds an implementation to get VBNV through the Chrome EC. We might want to refine this further in the future to allow VBNV in the EC even on x86 platforms. Will be fixed when that appears. Also, not all ARM platforms running ChromeOS might use the Google EC in the future, in which case this code will need additional work. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901 Reviewed-on: https://chromium-review.googlesource.com/167540 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6616 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13arm: libpayload: Add cache coherent DMA memory definition and managementJulius Werner
This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12libpayload: usbhub: Don't clear PSC unless it was setJulius Werner
The current USB hub code always clears the port status change after checking it, regardless of whether it was set in the first place. Since this check runs on every poll, it might create a race condition where the port status changes right between the GET_PORT_STATUS and the CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag before it was ever read. Let's add one extra if() to avoid that possible headache. Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168098 (cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6617 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12tegra124: Implement the monotonic timer by reading the 1us timer register.Gabe Black
It turns out there's a register in tegra which automatically counts at 1us increments. It's primarily intended for hardware to use (I think to drive other timers) but we can read it ourselves since a 1us timer is exactly what we need to support the monotonic timer API. Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172044 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6620 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-12tegra124: Add stack related config options to the Kconfig.Gabe Black
Otherwise the stack ends up down at 0 and has 0 bytes. Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171015 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12tegra124: Add some make rules which will wrap the bootblock in the BCT.Gabe Black
These rules slip into the normal bootblock preperation process and use the cbootimage utility to wrap it in a BCT. Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170924 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12gm45: Move S3 detection to enable stage.Vladimir Serbinenko
Also move it to NB to be in line with other. Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12i82801ix: Make RP04 optionally hotpluggable.Vladimir Serbinenko
Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Reserve RAM for ME if it's active.Vladimir Serbinenko
Change-Id: Icd2b075cec9461f9d6028a8c845f6900b6fe04c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6628 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Allow coexistance with ME firmware.Vladimir Serbinenko
Change-Id: I08ca5eec94c70b43789122266d68af149772385c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.ChromeOS Developer
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12exynos5420: minor clean-up memory related stuffDavid Hendricks
This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420/pit: re-factor membaseconfig0/1 usageDavid Hendricks
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420David Hendricks
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See <http://crosbug.com/p/20577>. This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
2014-08-12nvramtool: plug some memory leaksPatrick Georgi
Change-Id: I8f672b872862d3448ccd2cf28fd3c05b0108ff8b Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6561 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12Exynos5420: ddr3: fine tuning the DDR3 timing valuesDavid Hendricks
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.Julius Werner
The EHCI host controllers in Samsung Exynos SoC seem to be a little more picky than Intel ones. When they reach the dummy_qh in the periodic frame list, they try to access the next qTD pointer even though it's NULL, and run into a HostSystemError. This patch explicitly sets the Terminate bit on those pointers to mark them invalid. Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66884 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12Exynos5420: Remove code for enabling read levelingDavid Hendricks
This patch intends to remove all code which enables hardware read leveling. We need to disable h/w read leveling because new ASV table is merged in kernel (which is based on the new characterization condition) and new characterization environment has h/w read leveling disabled, so we should also disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly), improve LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. This was ported from: https://gerrit.chromium.org/gerrit/66070 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83 Reviewed-on: https://chromium-review.googlesource.com/66994 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6610 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12exynos5: Refactor board-specific parts out of USB PHY codeJulius Werner
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12libpayload: Make USB transfer functions return amount of bytesJulius Werner
The USB bulk and control transfer functions in libpayload currently always return 0 for success and 1 for all errors. This is sufficient for current use cases (essentially just mass storage), but other classes (like certain Ethernet adapters) need to be able to tell if a transfer reached the intended amount of bytes, or if it fell short. This patch slightly changes that USB API to return -1 on errors, and the amount of transferred bytes on successes. All drivers in the current libpayload mainline are modified to conform to the new error detection model. Any third party users of this API will need to adapt their if (...<controller>->bulk/control(...)) checks to if (...<controller>->bulk/control(...) < 0) as well. The host controller drivers for OHCI and EHCI correctly implement the new behavior. UHCI and the XHCI stub just comply with the new API by returning 0 or -1, but do not actually count the returned bytes. Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48308 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Updated the patch to support XHCI as well. Change-Id: Ic2ea2810c5edb992cbe185bc9711d2f8f557cae6 (cherry picked from commit e39e2d84762a3804653d950a228ed2269c651458) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6390 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12exynos5420: ddr3: Cleanup init to use constants for directcmdDavid Hendricks
The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants for accessing directcmd registers. Modify to use #defines where possible. This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I01567fc6941608a570832de97259c55e84942d01 Reviewed-on: https://gerrit.chromium.org/gerrit/66789 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12exynos5420: Alter init sequence as per recommendationDavid Hendricks
As per hardware recommendation, CKE PAD retention release must happen just before gate leveling enable and only in case of resume. Hence, this patch moves pad retention release from dmc_common.c to dmc_init_ddr3_exynos5420.c. In addition to this we are providing 125 (+3 extra being safe) times auto refresh to DRAM by sending REFA direct command. This is required because when CKE PAD retention release happens, self refresh mode of DDR3 is disabled. Hence, auto refresh 125 times. This is ported from https://gerrit.chromium.org/gerrit/#/c/65573 Note: Since WAKEUP_DIRECT does not go thru memory init, it should be safe to move CKE PAD retention out of bootblock.c. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866 Reviewed-on: https://gerrit.chromium.org/gerrit/66788 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6604 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12exynos5420: Make USB A-A booting work with early data cacheJulius Werner
Apparently the IROM doesn't like data caches... the recently added dcache-in-bootblock makes A-A booting fail, and flushes/invalidations alone don't seem to fix it. It's pretty fast anyway, so we just disable the cache again for the duration of the IROM call. Also removes a superfluous invalidation line from the bootblock code... dcache_mmu_enable/disable already take care of that. Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66602 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f) exynos5: Implement booting from SDMMC media This patch augments the alternative CBFS media source implementation for Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as an SD or uSD card reader, if available). It also moves MMC initialization for the Snow, Pit and Kirby boards from romstage to ramstage (mainboard_init) to prevent it from interfering with the IROM during SDMMC boot. Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66154 (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc) snow and pit: turn on FET4 (for SD card) at bootup Explictly enable FET4 on Snow and Pit. Historically we haven't needed to do this because: * On snow there's a bypass around FET4 which effectively eliminates it. Even if we don't turn on FET4 the SD card is still powered. Turning on FET4 doesn't hurt though and is technically correct. * On pit the EC turns on FET4 on cold bootup. On pit we run into a problem if the kernel turns off FET4 like in <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a software reset or warm reset. In this case the EC won't know to turn it back on. This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c Reviewed-on: https://gerrit.chromium.org/gerrit/66786 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646) Squashed three commits for alternate cbfs SD support. Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12util: replace fseek/ftell/rewind with fstatPatrick Georgi
It's a more direct approach to get the file size. Change-Id: If49df26bf4996bd556c675f3a673d0003b4adf89 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6594 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12board-status: be protocol agnostic on uploadPatrick Georgi
Generate the board-status repo URL by replacing the last occurrence of "/coreboot" by "/board-status", which works across repo URL schemes (gerrit provides several). Change-Id: Iccb53bde994be619c1436815e13741d63738edf7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6574 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12Kconfig: do not set SB_HT_CHAIN_ON_BUS0 twice to the same valueDaniele Forsi
Change-Id: If7286abf91f758cfbac2c85dcad336f38f70d843 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6579 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-08-12util/genprof: improve handling of command line argumentsDaniele Forsi
Accept only one command line argument (the input file name); close input stream both on error and on success; print more informative error messages when files could not be opened. Change-Id: Ib2f0622a332317d7a13f33f1e5787381804c43a9 Found-by: missing fclose()'s found by Cppcheck 1.65 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12armv7/Makefile.inc, cpu/Makefile.inc: align output of printfDaniele Forsi
Fix whitespace. Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12mainboard/intel/minnowmax: clean up includes & whitespaceMartin Roth
Clean up as requested in commit e6df041b. No functional changes. Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6597 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12cpu/intel/XXX/acpi.c: Fix coding style violationMartin Roth
Clean up a coding style violation as requested in the review of commit 09670265. Change-Id: I2815635efbb70a1e5841ca79cf2b4845bc6c23f2 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6598 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12gm45: Ensure that brightness register in gma contains sane value.Vladimir Serbinenko
Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6587 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf filesMartin Roth
The absf files contain the modifications to the default settings in the FSP. They are used as input files for Intel's 'Binary Configuration Tool' (BCT) along with the FSP.bin file to generate customized FSP binaries. The Minnow Max absf files set up the values for the soldered down memory. This requirement will go away with the release of the next Bay Trail FSP, and the memory settings will be configurable at runtime. Change-Id: Id72545d78a7e82d9a5090710a9c7a8a9b1e81208 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6432 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-11bayleybay_fsp: Add bakersport board variantMartin Roth
The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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