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2014-10-16amdk8: Move to per-device ACPIVladimir Serbinenko
Change-Id: I485791015aa7eaabba53813945c216f5725554b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-15i945: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-15gm45: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7039 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
Zero out the GNVS area so that uninitialized portions are defined. Tests using Microsoft Windows (XP/7/8) gave a bluescreen bugcheck: A5 (ACPI_BIOS_ERROR) with the first parameter (0x00001000) (ACPI_BIOS_USING_OS_MEMORY). Some ACPI enumerated devices use the GNVS area to define whether they're enabled and their MMIO regions. On my custom baytrail-based board and build, these devices were disabled but GNVS had uninitialized data indicating the devices were enabled with improper MMIO regions. Should investigate further to see where the GNVS device values are set if enabled and make sure they're set to valid values even when the devices are disabled via the mainboard/devicetree.cb. Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-11acpi: Don't add an empty SSDT.Vladimir Serbinenko
It's harmless but useless. Change-Id: Iaaa5f6933d120a2071b2e32e62e36e63afa96be3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7043 Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: build bot (Jenkins)
2014-10-11acpi: Remove explicit pointer tracking in per-device ssdt.Vladimir Serbinenko
It's useless and error-prone. Change-Id: Ie385e147d42b05290ab8c3ca193c5c871306f4ac Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7018 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-11bd82x6x, ibexpeak, lynxpoint: Declare NVSA before its use.Vladimir Serbinenko
Windows chokes if it's not the case. Change-Id: I3df15228ed00c3124b8d42fc01d7d63ff3fe07ba Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7017 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-10-11early section: Don't add empty .car.cbmem_console.Vladimir Serbinenko
With handling of this section removed it confused the linker. Change-Id: Id096c1642c0bfed1007a4b7d7dfa89f8b4ffcae1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7042 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-10-10via/epia-m: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic63fc1f933fff5cd58adcd4299c4ac2a62c4bb68 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6941 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-10lynxpoint: Change OEM table ID for serialio.Vladimir Serbinenko
According to ACPI spec all SSDTs should have distinct OEM table ID. We end up with 2 SSDTs named "COREBOOT". Fix this. Change-Id: I01bccb72758baf51c6b4263778716f4bb9d438c9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-10bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars.Vladimir Serbinenko
Change-Id: I672c3ca9e7f30a21330cf1920a25b1ab38b3f282 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-10acpi_create_mcfg_mmconfig: Zero-out the structure before filling.Vladimir Serbinenko
Otherwise "reserved" fields end up with a garbage instead of predictable value. Change-Id: I8a036769a8f86f1d6752651601de2800f4f1bd00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7014 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-09intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"Kayalvizhi Dhandapani
Fix the error 'implicit declaration of function "southcluster_smm_save_gpio_route"', when SMM module is added. Change-Id: Ia050ab7e2b036541537b645d3fe4dc747cd1dff8 Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7024 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-09intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module addedKayalvizhi Dhandapani
Change-Id: I6d8622c7f343619b915442d8056aa6672dfc4f6e Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7025 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-09intel/fsp_baytrail: Fix SMM/SMIKayalvizhi Dhandapani
With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-10-09AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.incBruce Griffith
The static library builder for the stub that interfaces to the AGESA binary does not include config.h and kconfig.h, so any header file changes that depend on Kconfig variables fail. Force these two system headers to be included in the build of any AGESA stub files. Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68 Reviewed-on: http://review.coreboot.org/6979 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-10-08xcompile: detect and use RISCV binariesRonald G. Minnich
RISCV is a new architecture. This change simply setups up xcompile to detect and use RISCV compilers if they are found. Change-Id: Iad1a88ef2e3c8dd1e601549aeca26fb29b2bc7ae Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-08mkelfimage: removeRonald G. Minnich
It's not been needed for years, is definitely not needed now that cbfstool parses bzImages, and its presence keeps confusing people. Also, rewrite history. We never mentioned mkelfimage in the documentation. Never, ever, ever. Change-Id: Id96a57906ba6a423b06a8f4140d2efde6f280d55 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7021 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-07edid: Relax EDID 1.3 requirements.Hung-Te Lin
In E-EDID (EDID v1.3), Monitor Name (0xfc) and Monitor Range Limits (0xfd) are always required. However, some panels do not really have these fields. As a workaround (and since we don't really use these fields), we only print warning messages for that case. Change-Id: I81b1db7d7f6c6f9320a862608dec4c7be298d7db Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193742 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit c633215ef8342664d9a4478e821fc8aad368b7f3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7009 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-07cbmem console: Locate the preram console with a symbol instead of a section.Gabe Black
On non-x86 systems, the location of the preram CBMEM console may not be in a predictable place relative to other things in the linker script. That makes it difficult to work with as its own section because the linker will complain if you try to move backwards as it lays out memory. If the console header is treated as an actual blob of memory which has to be put in the image, we'd have to predict where to put it so that it isn't before something with a lower address or after something with a higher address. Symbols, on the other hand, can be defined arbitrarily. Change-Id: I3257b981eee0c15bb997a9f2c55a03494c6ec6f0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/193164 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a492761c27076bcac080013d509ae4aafd6dc3e3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7013 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-07gen: Add "assert" in assert.h.Hung-Te Lin
Typically assert.h should provide assert(). Change-Id: I465f4a616b212f7b00d445c575866b13eecfa6fb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187410 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 3990584ac8e1ec9b3838bd9dfdf8a9cb2d20fbd0) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6961 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-07vendorcode: Add ChromeOS VPD parser.Hung-Te Lin
Copied (and unmodified) the minimal bits from ChromeOS libVPD: https://chromium.googlesource.com/chromiumos/platform/vpd Old-Change-Id: Id75d1bfd16263ac1b94c22979f9892cf7908d5e6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187411 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> (cherry picked from commit a10ca23686299f3fd5b639631242cadaa2ca9e8a) vendorcode: Update ChromeOS VPD Parser. Merge recent changes in ChromeOS VPD that allows non-memory-mapped firmware to load VPD easier and faster (ref: https://chromium-review.googlesource.com/188134 ). Old-Change-Id: I3ee0b89c703f476f3d77cdde52cc7588724f7686 Reviewed-on: https://chromium-review.googlesource.com/188743 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 03f4d521a7fa711b963b0e1822e92eac16a691b1) vendorcode: Access to ChromeOS VPD on default CBFS media. The new function "cros_vpd_gets(key, buf, size)" provides an easy and quick way to retrieve values in ChromeOS VPD section. Old-Change-Id: I38e50615e515707ffaecdc4c4fae65043541b687 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187430 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> (cherry picked from commit bcd3832c06e8ed357c50f19396da21a218dc4b39) Squashed 3 related commits for a ChromeOS VPD parser. Change-Id: I4ba8fce16ea123c78d7b543c8353ab9bc1e2aa9f Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6959 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-10-07sconfig: add cpu device typeAaron Durbin
In order to enumerate CPU devices that are non-x86 (read: no lapic) provide a generic 'cpu' device. Change-Id: Ifeafdad8076935c3448784e6958117002509acbf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-04Kconfig: Allow native vga init to be selectable for SeaBIOS payloadEdward O'Callaghan
Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6891 Tested-by: build bot (Jenkins) Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-04mainboard/amd: Sanitise headers in PlatformGnbPcie.cEdward O'Callaghan
It is hard to see where things are coming from without correct headers. Change-Id: I8e2195b101501ffd25464196283fb2bddb5b8f51 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5980 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-02Provide a way to compile some files with -O0 optionVadim Bendebury
When preparing an image for source level debugging, it is convenient to be able to compile some modules with -O0, which makes it much easier to follow the execution flow. This patch allows to do it by defining GDB_DEBUG=1 in the environment before invoking make. Adding this feature as a common config flag is problematic, because we don't want to compile the entire image with -O0. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196359 (cherry picked from commit dde4928c045d12e502cb109015a710cd9fdf2a04) Changed from CFLAGS to CFLAGS_common. Change-Id: Ie0be653509509eeb64ea3a7229f54c0c812840a9 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-02elog: Add event type for CPU thermal tripDuncan Laurie
There is a status bit for this event in most intel chipsets that we can read and report. Start by adding the new event type. Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 386a06170ec5afb31d0fe93ace3afbaab897a598) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7004 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-02libpayload: usb: xhci: Treat port reset as a port status changeShawn Nematbakhsh
If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-02libpayload: usb: Remove generic roothub reset port functionShawn Nematbakhsh
The generic roothub reset port function is overly broad and does some things which may be undesirable, such as issuing multiple resets to a port if the reset is deemed to have finished too quickly. Remove the generic function and replace it with a controller-specific function, currently only implemented for xhci. Change-Id: Id46f73ea3341d4d01d2b517c6bf687402022d272 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189495 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 54e1da075b0106b0a1f736641fa52c39401d349d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-02nvidia/cbootimage: avoid upstream's build systemPatrick Georgi
It brings in useless dependencies, a weird autotools configuration, and tons of pain everywhere. Instead just build things ourselves. Change-Id: I67f06e711cb9dcd594363bc1a4f99d3273074549 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6986 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01baytrail: update C0 microcodeShawn Nematbakhsh
baytrail: Add 811 microcode for C0 parts Incorporate 811 microcode version for C0 stepping parts. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d Reviewed-on: https://chromium-review.googlesource.com/191693 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594) baytrail: Add 813 microcode for C0 parts Incorporate 813 microcode version for C0 stepping parts. Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c) baytrail: Update microcode to version 816 Version 816 of microcode. Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364 Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e) Squashed 3 successive updates for baytrail C0 microcode. Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01intel/i945: Another magic numberPatrick Georgi
Replace it with the existing #define Change-Id: I6e67ed1a455cd4f9eeed1865b9ef981e7ef0a874 Found-by: Idwer Vollering Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6992 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-10-01intel/i945: Fix "always false" statementPatrick Georgi
Also replace magic number with already existing #define Change-Id: I64d22aca185bf43ff0ac126584b41920182a1112 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6990 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-10-01reg_script: Fix bug in IO macrosDuncan Laurie
These have apparently never been used because they are incorrect. Change-Id: I3624cb2548a0ee3da56a2cca62ed50b0dfbf7817 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196266 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit bc0187702061fe326422c070c592a18cd93de723) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6999 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01edid: Support EDID 1.4.Hung-Te Lin
EDID v1.4 has changed some fields (0xfc - Monitor Name, 0xfd - Monitor Range Limits) to optional so we need to list the requirements explicitly instead of sharing v1.3 requirements. Change-Id: I5c7ca06893bd20e178bc35164c4ca639c881e00b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193013 (cherry picked from commit 2ad598b8bd620117e70e13347365d74a7c6b87ef) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01edid: Accept valid detail blocks without timing descriptor.Hung-Te Lin
The detail block may contain timing descriptor, or other fields like monitor descriptor, so we should return 1 in detailed_block function when a valid structure is found, otherwise for any EDID containing monitor descriptor we will see following error messages: EDID block does not conform at all! Detailed blocks filled with garbage Change-Id: Ib4e91d648741e5b54a558d53a1152273c7341427 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193002 (cherry picked from commit a1f212d6aaa14d5f795beeabdb8b7b8a79578c33) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6997 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01edid: Fix string extraction in Monitor Descriptors.Hung-Te Lin
The ASCII Data String in EDID Monitor Descriptor (3.10.3) is "Stored as ASCII, code page #437" and may contain special characters like '-'. The isalnum check should be removed. Also, the "Monitor Name" (0xfc) does not need to always end with 0Ah, so the name_descriptor_terminated should be replaced by has_valid_string_termination. Change-Id: I12a670237e12577fc971c0fbd9b2a61c82040ad3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193001 (cherry picked from commit 671f82fd5963e32e72d3886aa242cb3e8519f226) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6996 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01storm: Add generic support skeleton for stormFurquan Shaikh
Skeleton for storm mainboard Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190724 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit ba371d410768fae169da929a23c40139d26a55d3) Removed 'select ARCH_ARM' and added 'select BOARD_ROMSIZE_KB_1024' to the Kconfig. Change-Id: I55c0ad6a47515ba4124b99a69d5776db2365f06e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6975 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-10-01edid: Fix extension parsing when EDID blob does not have any extensions.Hung-Te Lin
When parsing "extensions", we should skip the first EDID (main) block and start from offset 128 (EDID may have only main block, so an EDID without any extension is fine) because the header format for main block and extensions are different. Without this we will see "Unknown extension block" on all EDIDs, and seeing an error (1) return value for EDIDs without extension. Also, after the first "unknown" error is fixed, we can now collect all return values from parse_extension, and return an error when any of the extensions are wrong (not just last one). Change-Id: I0ee029ac8ec6800687cd7749e23989399e721109 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193011 (cherry picked from commit fdf0cc2e9573c19b550fa2b5e4e06337b114f864) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6995 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-01edid: Fix source indent.Hung-Te Lin
Some lines in decode_edid have incorrect indent levels. Change-Id: Icc9cb57ff8dd2e2056599b3dc733fe5ac4e41c16 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193010 Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3211ac0a29a037c5414f9ed1736c8f7822ad116b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6994 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-29google/panther: add board_info.txtMatt DeVillier
Change-Id: Iec0397a981c31c8af3def04b8c170884f79a50cc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6871 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-29intel/minnowmax: Enable S3 suspend/resumeMohan D'Costa
This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6972 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-09-29intel/fsp_baytrail: Add S3 suspend/resume SupportMohan D'Costa
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-09-29spi: Add support for Winbond W25Q128FWMohan D'Costa
The W25Q128FW spi part is programatically equivalent to the other W25Q128 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. Tested on a modified MinnowMax Board. Change-Id: Id6a426418a7f785a9d959b02a9e3d2ffc421804f Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6971 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-09-29asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in commentPaul Menzel
Change-Id: If50685505143ccbd51098e92de72545c71b24892 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29libpayload: Build libpayload with debugging info turned up all the way.Gabe Black
Pass -ggdb3 to the compiler when building libpayload, -ggdb so that it uses "the most expressive format available", and 3 so that the debugging level is set to 3, the highest value currently supported. The debugging information can be stripped by the payload consuming the library, and will definitely be stripped by cbfstool when installing that payload into an image. Change-Id: Ifd6c4a928fbb0b9fa9b3b2e0ea298abff31baf3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/180252 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit dc04daaf099c53c57508b66e08f40945345a56ca) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29Remove stale char[] initialization causing unaligned memory accessMarcelo Povoa
This throws an alignment fault when run in ARMv8 Foundation model and seems unnecessary, so remove it. Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186744 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6974 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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