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2019-07-04amdfam10: Declare empty activate_spd_rom() stubKyösti Mälkki
Change-Id: I1d0940a08f7ae5901b812618a6859c4297274591 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-03soc/amd/common/lpc: Add Picasso IDMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/common/iommu: Add Picasso IDMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/common/hda: Add Picasso IDsMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove all PSP runtime functionsMarshall Dawson
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove fanless SKU optionMarshall Dawson
The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/picasso: Remove SD controllerMarshall Dawson
Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03soc/amd/picasso: Add xhci1 and remove ehciMarshall Dawson
Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03soc/amd/picasso: Remove most stoneyridge USBMarshall Dawson
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove stoneyridge GECMarshall Dawson
Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Change all remaining soc namesMarshall Dawson
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03util/cbfstool: Add AMD BIOS compression tool for PSPMarshall Dawson
Add a utility to generate a compressed BIOS image for AMD Family 17h. If the input is an elf file, the utility extracts the program portion for compression. Otherwise the file is compressed as-is. In modern AMD systems, the PSP brings up DRAM then uncompresses the BIOS image into memory prior to x86 beginning execution. The PSP supports a zlib engine, and interprets the first 256 bytes as a header, where offset 0x14 containing the uncompressed size. For further details, see AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:127766506 TEST=Use with WIP Picasso Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-03aopen/dxplplusu: Replace use of dev_find_slot()Kyösti Mälkki
To use fixed PCI bus numbers is always invalid. Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-03aopen/dxplplusu: Remove PIRQ tableKyösti Mälkki
It was never tested or injected. Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03intel/e7505: Drop debug codeKyösti Mälkki
Only (conditionally) used part was dump_pci_device() and that was never particularly useful either. Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-03soc/intel/skylake: Add Kabylake-R microcode update filesArthur Heymans
This also corrects some CPU naming in comments. Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMIKevin Chiu
garg 2A2C DB: SKU ID - 1 garg HDMI DB: SKU ID - 9 garg LTE DB: SKU ID - 17 For HDMI SKU9, GPIO needs to be overriden to enable DDI1 DDC SDA/SCL. BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-07-03mb/google/octopus/variants/fleex: Enable EMR function for Grob360SChris Zhou
Enable EMR Pen Stylus function for Grob360S BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with HW reworked Fleex. Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33802 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03mb/google/octopus: Add custom SAR values for BlooguardTony Huang
Google project name is Bloog. Bloog is 12-inch LCD. Blooguard is 14-inch LCD so would prefer to use a different SAR values instead. Use sku-id to load the SAR values. BUG=b:135078377 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-03vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platformsJulius Werner
When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on some Arm platforms the original working data buffer was in SRAM, which stays accessbile for the whole runtime of the system. There is no reason to migrate it into CBMEM on those platforms because ramstage and the payload could continue to access it in SRAM. Now that we've had a couple of months of experience with this option, we found that most of our Arm platforms have some issue that requires migrating anyway, because BL31 often claims SRAM for itself and makes it inaccessible to the payload. On the remaining platforms, accessing SRAM from the payload is possible but still an issue, because libpayload doesn't have enough memory layout information to set up proper page tables for it, so we're accessing it uncached and at risk of alignment errors. Rather than having to figure out how to map the right SRAM range for every platform in the payload, let's just get rid of the option. memcpy()ing 12KB isn't worth this much hassle. Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-02sdm845: Update macro definition in CB clock driverAkash Asthana
Use literals KHz & MHz for kilohertz and megahertz frequency usages in macro definition. Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02arch/x86: Fix spelling error in BERT commentMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02cbfstool: show "preserved" flag in cbfstool layout outputPatrick Georgi
The flag is useful for updaters to determine which areas to leave alone, such as VPD (vital product data) regions that are set in factory and might contain unique (MAC addresses) or hard to obtain (calibration output) data. It's also useful to see which regions are marked as such. Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02cpu/amd/msr: Clarify MMIO_CONF shift valueMarshall Dawson
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field. Change it to simply 2. Otherwise its usage winds up evaluating to BusRange << (1 << 1). Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02libpayload/usb: Increase USB request timeout to 5 sKeith Short
Increase the timeout for USB requests to 5 seconds for all USB host controllers. Prior to this fix, the xCHI driver was detecting false timeouts during SET ADDRESS requests when nested downstream hubs were connected to the xHCI root hub. BUG=b:124730179 BRANCH=sarien TEST=Build libpayload and depthcharge on sarien/arcada. TEST=Without change replicate USB set address timeouts in depthcharge when dock and 4K monitor connected (which includes a total of 4 USB hubs). With timeout fix, depthcharge boots OS with no USB errors and the same USB topology. Note that this tests xHCI operation only. Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-02arch/riscv: Make RISCV specific options depend on ARCH_RISCVArthur Heymans
Also don't define the default as this results in spurious lines in the .config. The only difference in the generated config.h is that for most board ARCH_RISCV_M goes from 1 to 0. This should not matter. Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02drivers/pc80/rtc/mc146818rtc_boot: Use size_t for lengthElyes HAOUAS
Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-02src: Use CRx_TYPE type for CRxElyes HAOUAS
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/intel/cannonlake: Add support to log XHCI wake eventsPaul Fagerburg
Enhance elog wake source information with more details about which USB port resulted in a wake from S3 or S0ix. BUG=b:123429132 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Plug a keyboard into a USB port on the DUT. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). On the console, run ``powerd_dbus_suspend``. Wait for the DUT to enter low power mode. Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. Press a key on the USB keyboard. The DUT wakes up. On the console, run ``mosys eventlog list`` and look for the wake source. 156 | 2019-06-26 09:46:07 | S0ix Enter 157 | 2019-06-26 12:14:05 | S0ix Exit 158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0 159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109 Program image-hatch.serial.bin into the DUT using flashrom. Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list`` sequence. 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-02util/cbmem: Enable -Wmissing-prototypesJacob Garber
Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02util/cbmem: Make internal functions staticJacob Garber
These functions are only used in cbmem, so they can be made static. Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02util/cbmem: Enable -WextraJacob Garber
This enables extra useful warnings. Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02util/cbmem: Use correct integer types for loop indicesJacob Garber
Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-023rdparty/fsp: Update submodule pointerBora Guvendik
Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40 github commit: https://github.com/IntelFsp/FSP/commit/59964173e18950debcc6b8856c5c928935ce0b4f Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02arch/x86: Fix cpu_cpuid_extended_level() return typeElyes HAOUAS
`cpuid_eax()` returns an unsigned integer. Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-02util/docker/coreboot.org-status: Add more "nice" names for CPUsPatrick Georgi
It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework. Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02util/release: add more categoriesPatrick Georgi
Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02mb/google/hatch: Set trackpad irq and wake to GPP_A21Shelley Chen
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad.\ 3. Run "echo mem > /sys/power/state", wait until device goes into S3, click trackpad to ensure device wakes. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-02mb/google/hatch: Add INVERT to all IOAPIC padsShelley Chen
Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by clicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd: Add picasso to KconfigMarshall Dawson
Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33750 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd/picasso: Stub out bootblockMartin Roth
Remove all Picasso bootblock support. CAR is not a supportable feature, and the first code executed at the reset vector will be a hybrid romstage. Details for this implementation may be found in Documentation/soc/amd/picasso/family17h.md. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Update stoney paths to picassoMartin Roth
Update paths. There are still a few paths in Kconfig relating to PSP and the firmware directory table. Those will be updated in a follow-on commit. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd/picasso: Rename makefile.inc back to Makefile.incMartin Roth
Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18ee48865fb64265f38179560265827783d50820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSOMartin Roth
TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32410 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd/picasso: Change header guards from stoney to picassoMartin Roth
TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Remove ST files not used for PCOMartin Roth
Remove files that aren't needed for the picasso port. Remove traces of AGESA v5 (includes binaryPI support files). Remove SPD helper. Picasso (and all AMD Family 17h processors) have a very different boot flow from previous products. Memory is initialized by the PSP before the x86 processor is released from reset. The SPD is read by the PSP, so it's not needed in coreboot. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-02soc/amd/picasso: Create picasso as a copy of stoneyridgeMartin Roth
So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ densityKevin Chiu
Samsung K4F6E3S4HM-MGCJ density is 16Gb BUG=b:121228792 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage MemTotal: 8041964kB in /proc/meminfo Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02device/pci_rom: Fix redundant pci_rom_probe() callsKyösti Mälkki
For the PCI_VENDOR_ID_ATI case, we can rely on pci_rom_acpi_fill_vfct() to make the call if necessary. For hardware other than ATI, pci_rom_probe() was already called from pci_rom_ssdt() and pci_dev_init(), so PCI_ROM_ADDRESS BAR is already enabled, if requested so. Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02device/pci_rom: Fix on-board optionrom addressKyösti Mälkki
The function pci_rom_probe() may be called multiple times for a device. For cases where CBFS does not contain optionrom file, only the first time probing for the on-board ROM chip worked. PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all the reserved bits of PCI_ROM_ADDRESS register to get correct physical address for rom_header. Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 10:23:30 +0000