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Change-Id: Ic8ffd26e61c0c3f27872699bb6aa9c39204155b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16390
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16433
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
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Align the column of comments.
Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16427
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A recently announced Turbot system populates two Ethernet
controllers. Enable the remaining disabled PCIe port.
Also add a clarifying comment regarding the port associated
with Function 0. Coreboot must not be allowed to disable the
function which breaks PCI compatibility.
Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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MinnowBoard Turbot systems have a GPIO-controlled LED that is
generally used to indicate the CPU is running. Commit 2ae9cce8
changed the parameter for GPIO_NC, exposing an issue with the
assumed behavior of the signal. Use a pull-down to turn on the
LED.
Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16428
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Taken from upstream Linux kernel.
Change-Id: Id8c9d48b8ca3c7592dc4d78cfd092714bbbb2abf
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Replace the use of the old device_t definition inside
northbridge/intel/i945.
The patch has been tested both with the arch/io.h definition of
device_t enabled and disabled in order to ensure compatibility
while the transaction takes place.
Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16371
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__
in order to account for the coreboot stages that do not define device_t
and are not __PRE_RAM__ (i.e. smm) device_t
Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16369
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Replace the use of the old device_t definition inside
northbridge/intel/sandybridge.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16409
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Avoid the inclusion of a function declaration if the argument type
device_t is not defined.
This was not a problem until now because the
old declaration of device_t and the new one overlapped.
Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16404
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Replace the use of the old device_t definition inside
southbridge/intel/bd82x6x.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16407
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Indent the I2C device for touchscreen with tabs so it
aligns properly.
Change-Id: Id9b2d26a4acdd6fe6c69055907258df3cc035b31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers
New boards would then add themselves under their board name
within the 'variants' directory.
No split has been done with providing different logic yet.
This is purely a organizational change.
BUG=chrome-os-partner:56677
Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.
BUG=chrome-os-partner:56677
Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The superio.asl wasn't being included within the right scope.
Fix that as well as clean up the per-mainboard header includes
to be in one place.
BUG=chrome-os-partner:56677
Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16413
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
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Some of the macros in gpio.h are no longer used because
devicetree.cb is being used to autogeneric the ACPI AML.
Therefore remove the unused macros.
BUG=chrome-os-partner:56677
Change-Id: I433a929229a0318f6c1df652655d046a5152cc63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16412
Tested-by: build bot (Jenkins)
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Commit 93ef3ff makes the following only print the part number when
the ROM is built. In Makefile.inc, $(MAINBOARDDIR) is the variable
that has the quotes stripped off from $(CONFIG_MAINBOARD_DIR), so
use it instead of $(MAINBOARD_DIR).
build_complete:: coreboot
printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \
$(CONFIG_MAINBOARD_PART_NUMBER)
Change-Id: I729a583182937db7a926eb75aa28dfb53360046c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/16410
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16391
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Antonello Dettori <dev@dettori.io>
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Increase the default timeout in the LPSS I2C driver to 4ms
from 2ms. During testing with some slower devices I found
that the existing timeout could be too short leading to
transaction failures.
Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16392
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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- Don't require a description of every config statement in the
Kconfig changes
- Don't complain about externs in .c files
- Don't complain about the use of the volatile keyword. The kernel
may not want it, but we definitely need it.
- Disable checks that seem to be broken.
Change-Id: Ic419b81cd36852a91e887e610d4a04984ab5fbd7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Change-Id: I387603aff6efd6da5e9d78f204d94c064a99e1d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
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FSP header files should be located in vendorcode, not soc directory.
This patch includes changes any references to the old location to
the new location.
Change-Id: I44270392617418ec1b9dec15ee187863f2503341
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add UDK 2015 Bindings for FSP header compatibility.
These bindings add the necessary code to read FSP Headers
without any modifications from FSP Source.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image and verified boot
Change-Id: I2887f55b6e63cd0a2b2add9a521be9cfaf875e7d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32
which cannot be read using read_le32(&returnval). Add in a
cast in order to safeguard for any non x86 architecture that may
use this relocate. The proper change will be to get the UEFI
header files changed to not cast this return value.
Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Replace the use of the old device_t definition inside
mainboard/lenovo/x60.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Commit ba28e8d7 (src/southbridge: Code formating) incorrectly inserted
some whitespace in these files.
Change-Id: Ifdcc3580aaba224a396c6efec319e22610c6c81d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16385
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Uses gpio.h instead of default_southbridge_gpio_setup to configure
southbridge GPIO's. This is more consistent with how GPIO's are
configured on newer targets.
Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16379
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The checksum command might appear to be unpredictable only by
checking the OS. Just list the candidates, sorted by possibility.
Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/11483
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
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Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO
community names, follow one single convention. This allows for re-using
macros easily.
Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16353
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove an undeclared variable that was accidentally left over,
nvramcui is currently unable to compile and operate because of this.
Regression introduced in: 904dd303cbe99541025cbea008855f807a5d9f5c
(nvramcui: refactor code)
Fixes: https://ticket.coreboot.org/issues/70
Change-Id: Ieaba615838d7593546ab5696baf1b8f9828da345
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Many changes make proto boards very hard to work with since
proto boards were using A stepping processors. Everyone has
moved on. Therefore, drop non-proto support.
BUG=chrome-os-partner:56791
Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16377
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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A pen interface was added. Prepare for possibly testing it by
plumbing in the gpio configuration. It's very possible these
changes need to be tweaked, but no driver code has been seen
yet nor a datasheet detailing how some of these signals actually
function.
BUG=chrome-os-partner:56739
Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16376
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The formerly name FP_INT_L net is actually active high and is push-pull.
Therefore adjust for the new net name, FP_INT, and polarity. The
pulldowns are there because the device is on another board that isn't
always available.
BUG=chrome-os-partner:56740
Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16375
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Two new SKUs are being utilized for reef DVT. Add the following:
Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100
Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101
BUG=chrome-os-partner:56738
Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The reef DVT build added another way to assert the wifi module's
reset line. Ensure it's deasserted by default. For previous boards
this GPIO doesn't matter because it wasn't routed anyway.
BUG=chrome-os-partner:56737
Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The recent changes to this file from commit 6e5421d2
(sb/amd/sb700: Add option to increase SPI speed to 33MHz)
were accidentally removed in a code cleanup patch:
commit ba28e8d7 (src/southbridge: Code formating).
Change-Id: I6cf3e8f29d5c0384d35637f35e051be40318d20f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16384
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins)
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Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.
With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.
This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.
BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board
Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16304
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I013f71b702644ab337c3d76be1489530bad6e6cc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16322
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5b69a8429eb2f7add08bc134d5d2366a1afe6a4f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16343
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16321
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic644cf6792a5d360527e48e04c74ae92be0d1d4f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ibb2ce383322c174bdb3bcc88ae35c17f179f6d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16323
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c
The intel documentation on i945, "Mobile IntelĀ® 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.
The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.
What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.
TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version
Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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