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2018-07-24util/crosgcc: Fix most shellcheck errors in buildgccMartin Roth
This fixes most of the simpler shellcheck errors in shellcheck 0.4.6. There are still a few warnings left that weren't simple to fix or would have required more testing before I was confident in them. Change-Id: I79ab3614cc1d69d3dfe1e0374e930313f2011cbf Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24util/crosgcc/patches: update make-4.2.1 patchesMartin Roth
- Add the Do-not-assume-glibc-glob-internals patch to fix segfaults. - Update glob_interface_v2 patch to the patch directly from the make git repository instead of translating it. This gives better attributution to the original author. Change-Id: Ibc936fc00925a4ca2170a6f5dca7c2b8d8d62f02 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24Build system: Add fixes for scanbuildMartin Roth
- Exclude build flags that generate warnings when scanbuild is running - Add the SCANBUILD_ARGS variable to abuild so we can pass in arguments to scanbuild. - Set the default scanbuild argument to -k (--keep-going) so that even if an error occurs it continues with the scan. This is similar to what we do with coverity runs. Change-Id: I82e7c13d7fd7432b43c17a31834ec82fca158a07 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24util/docker: Update Makefile to improve shell accessMartin Roth
- Create a new target, docker-jenkins-attach, to access the running jenkins server - Update docker-shell target to set term & size. Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27494 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-23mb/google/kahlee: Update i2c timingsMatt Wells
Change the I2c timings to the latest measurements. BUG=b:72442912 TEST=Boot grunt Change-Id: I6f9538d26b77ae952ad585e569b3a836e1a09da2 Signed-off-by: Matt Wells <dawells@google.com> Reviewed-on: https://review.coreboot.org/27553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-23mb/google/poppy/variants/rammus: Add support for rammus boardZhuohao Lee
This change adds variant rammus derived from baseboard poppy. The setting is copied from the poppy and will be modified later BUG=b:111579386 BRANCH=master TEST=emerge-rammus coreboot Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-23mb/apple/macbookair4_2/Kconfig: Don't select VGAArthur Heymans
CONFIG_VGA is only used with C native graphic textmode. Change-Id: Iafa9e96fd001cd148889ef534e6499f562e7dec6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27530 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-23AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki
These are single-node platforms with CONFIG_CBB==0 everywhere in the tree. Remove guarded code that was not built. Change-Id: I6118249937e6c8032acd78018c7c83b1da078f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-23soc/cavium: Enable DRAM testPatrick Rudolph
Enable fast or extended DRAM test based on devicetree setting. The fast DRAM test takes less than a second, while the extended runs about 1 minute. Tested on Cavium Soc. Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-23soc/cavium: Apply additional devicetree fixupsPatrick Rudolph
Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings * Remove disabled PEM entries * Remove phandle to disabled PEM entries Fixes: * Linux console wrong baud rate once the PL011 driver is started. * thunderx-pem kernel module crash on disable PCIe ports. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-23mb/google/octopus: Add support for smbios_mainboard_skuFurquan Shaikh
This change provides implementation of smbios_mainboard_sku that queries the EC for SKU ID using CBI. Currently, get_board_sku() is implemented as a common function for all variants since this is the only way used by all the octopus variants to query SKU ID. If this changes in the future, this function can be changed to a variant_* callback. BUG=b:111671163 TEST=Verified following on phaser: 1. "mosys platform sku" returns the SKU ID programmed in CBI 2. "dmidecode -t 1" shows SKU information as "skuXYZ" where XYZ is the SKU ID programmed in CBI. Change-Id: Ic0d344b3c13632f2ca582adc36aa337b99959712 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-23mb/google/octopus: Use unused space in RO_SECTION for COREBOOT regionFurquan Shaikh
This change increases COREBOOT region size by the amount of unused space left in RO_SECTION. This extra space is useful when building images with debug enabled. BUG=b:111661025 Change-Id: Icbd88c3350f96707f37b69fe01f8ae9c7838ab82 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27555 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-22mb/asrock/g41c-gs: Add g41m-gs variantArthur Heymans
This board is quite similar to the other ones in this dir an can be supported with little code changes. TODO what works: * DDR2 dual channel PC2-6400; * SATA; * USB; * Ethernet; * Audio; * Native graphic init; * SuperIO Sensors; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot); TODO how tested: Tests were run with SeaBIOS and Debian stretch, using Linux 4.9.65. Change-Id: I6844efacaae109cf1e0894201852fddd8043a706 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-22mb/asrock/g41c-gs: Add the revision 1 variantArthur Heymans
Both g41c-gs and g41c-s can be supported by the same code since the only difference is ethernet NIC. What is tested: TODO: components How tested: TODO: payload + OS Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-22superio/nuvoton/npcd378: Fix resource sizePatrick Rudolph
Based on vendor ACPI code. Change-Id: I4d6785efb9d18953042775e7164710ef3c041ed5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-22mb/google/nautilus: Enable camera module NVMAlan Chiang
Enable DW9807 NVM support by adding required ACPI code BUG:b:110815821 TEST=On Nautilus board, execute "cat /sys/bus/i2c/devices/i2c-INT3499:00/eeprom" in the terminal and see if there is any data to be dumped. Change-Id: Ib83fa1a522402a59566e3f55fa5c1af4490266e4 Signed-off-by: Alan Chiang <alanx.chiang@intel.com> Reviewed-on: https://review.coreboot.org/27508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-22mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2#Seunghwan Kim
Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route,then abnormal over-current is asserted on USB type-A port. It causes USB type-A port to be blocked, so we need this internal pull-up. BUG=b:111578984 BRANCH=poppy TEST=Verified over-current not triggered abnormally on basic sku board Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-21mb/hp/compaq_8200_elite_sff: Add data.vbtPatrick Rudolph
Change-Id: Idb65d6c2ec85f09b8e7e9967ba0a055f876378df Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-21google/lars: Convert to a variant of gladosMatt DeVillier
Convert lars to a variant of glados Skylake reference board: - add lars-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add conditional generation of NHLT ACPI data for Maxim codec, including override of OEM ID and OEM table ID - remove existing lars board/directory Test: build/boot google/lars, verify functionality unchanged from pre-variant configuration Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27413 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-21google/chell: Convert to a variant of gladosMatt DeVillier
Convert chell to a variant of glados Skylake reference board: - add chell-specific DPTF, EC config, USB port defs, GPIO config, NHLT config, PEI data, VBT, SPD data, and devicetree - add romstage handler to turn on keyboard backlight for boards so equipped - remove existing chell board/directory Test: build/boot google/chell, verify functionality unchanged from pre-variant configuration Change-Id: I7dfbafe3afcab7cee7bcb2bf91c6733c07b409c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-21google/glados: Convert to variant setupMatt DeVillier
Convert Skylake reference board glados to variant setup in preparation for merge with existing Skylake boards chell and lars, and upstreaming of new boards asuka, caroline, cave, and sentry. The following changes have been made: - move DPTF to variant subdir - move non-common EC defs to variant subdir - adjust Kconfig for variant setup - move non-common NHLT config to variant Kconfig - make non-common NHLT ACPI code conditional - move devicetree to variant subdir - move board GPIO defs to variant subdir - move board PEI data to variant subdir - move SPD index calculation to romstage so available for dual-channel determination during PEI for boards which need it - move SPD compilation to variant makefile - add weak function for determination of dual-channel RAM - add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants can override and power down rails as needed Test: build google/glados Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-21nocturne: enable GEO SARPratik Prajapati
Enable the GEO SAR feature for nocturne. OxM programs wifi_sar VPD key in factory. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:65155728 BRANCH=none TEST= Set the wifi_sar VPD with below command (values are junk for test purpose only, actual values would be set be OxM) sudo vpd -f <coreboot.rom> -s wifi_sar=30313233343536373839303132333435363738393030313 24142433435364445463031324142433400364445463031323343444546303132333435 Flash the <coreboot.rom> and boot to kernel. Get ACPI table and WGDS would get created with VPD values passed in. Change-Id: I32ad591f15fdb34704c8d98d98646dfa2d8882ff Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-20AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki
With nodeid<8, CONFIG_CDB==0x18, PCI device number does not overflow. CONFIG_CDB is not a value we can configure. Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-07-20util/cbfstool: fix build with clangPatrick Georgi
Without the second set of braces it fails (due to -Werror) with "suggest braces around initialization of subobject" Change-Id: I63cb01dd26412599551ee921c3215a4aa69f4e17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27551 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20Documentation: update draft git commandTom Hiller
refs/drafts/master is deprecated Change-Id: I9c68e496ecd47fb559dd2ad400406007028cbb24 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/27526 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: Marc Jones <marc@marcjonesconsulting.com>
2018-07-20mediatek/mt8183: Add GPIO supportPo Xu
This patch implements gpio_set_pull() and links the common MediaTek GPIO code to support IO config for other drivers (ex. SPI) and the requested functions in src/include/gpio.h. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/27417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mediatek: Share GPIO code among similar SOCsTristan Shieh
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mb/google/poppy/variants/nocturne: set nvme to use clk src 3Nick Vaccaro
Latest nocturne architecture uses clk src 3 for nvme. BUG=b:111514174 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme nocturne devices are able to recognize the nvme controller. Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27536 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20libpayload/arm64: Drop unused static arrayPatrick Georgi
Fixes build with gcc8.1 Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mainboard/google/kahlee: Create Liara variantMartin Roth
This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20mainboard/google/kahlee: Create Aleena variantMartin Roth
This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20write_tables: return a pointer to the tableRonald G. Minnich
The write_tables function was void. It is a bit more useful for loading payloads from the romstage if it returns a pointer to the table it creates. Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/27537 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19util/gitconfig: Make checkpatch non fatal in pre-commit hookMartin Roth
We don't block commits for failing checkpatch in gerrit, and we shouldn't block them here. This allows checkpatch to still run, so users can see the issues, but won't prevent the commit. Adds a delay if checkpatch fails so that the issues can be seen. Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/27534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-19ec/lenovo/h8/acpi: Apply state on wakePatrick Rudolph
Implement ACPI S3 resume control to restore the state before entering sleep. * Store the requested state wake state for bluetooth and WWAN. * Add new methods to init the state and apply the requested state on wake. * Call the new method on all devices. Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add UWB ACPI interfacePatrick Rudolph
Add ACPI methods GUWB and SUWB for thinkpad_acpi. Required for power control of the UWB module. Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add keyboard backlight interfacePatrick Rudolph
Add methods MLCG and MLCS for thinkpad_acpi kernel module. Required for backlight or thinklight control from userspace. Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/acpi: Add WWAN ACPI methodsPatrick Rudolph
Implement GWAN and SWAN for thinkpad_acpi kernel module. Both methods allow power control of the WWAN module. Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19mb/lenovo/x201: Allow use of libgfxinitArthur Heymans
Tested on LVDS (internal), VGA and HDMI (on the dock DP++ connector) output with both native resolution and textmode. Change-Id: Ibfcb586d7b4cac7f1d22540bb96c288704a277a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27513 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19drivers/intel/gma: Default to LVDS for Internal on NEHALEMArthur Heymans
Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not support eDP, therefore default to LVDS. Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27512 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19soc/cavium: Add PCI supportPatrick Rudolph
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19payloads/LinuxBoot: Add ARM64 supportPatrick Rudolph
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures. * Always compress kernel Image using xz * Create FIT uImage containing the kernel, initramfs and DTB * Add ARM64 defconfig for all SoCs Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-19device/pci: Add MSI-X helper functionsPatrick Rudolph
Basic PCI MSI-X table helper functions. Imported from GNU/Linux kernel PCI subsystem. To be used on Cavium to configure MSI-X tables. Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26329 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19arch/x86/smbios: Add support for table 38Patrick Rudolph
Add support for SMBIOS table 'IPMI Device Information' and use it on HP Compaq 8200 Elite SFF. Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans for IPMI compatible devices. Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25386 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19Kconfig: Add config to insert ucode address in second FITRizwan Qureshi
This config is used to provide the name of a region where a microcode is located. The address of this will be added as the first entry in the FIT of the topswap bootblock. This adds a capability to associate two microcodes for each of the two bootblocks, this allows for the CPU to boot with different microcodes with 2 separate bootblocks. Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-19Kconfig: Add config for creating a second bootblockRizwan Qureshi
Intel PCH/Southbridges have feature that it is possible to have the southbridge/PCH look for the bootblock at a 64K or 128K/256K/512K/1MB (in case of newer SoCs) offset instead of the usual top of flash. Add configs to create a second bootblock and configure its size. Change-Id: I4bbd19c35871891b762a0673f840858d972e129e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19cbfstool/add-payload: initialize segment headers to 0Joel Kitching
Some types of payload segment headers do not use all fields. If these unused fields are not initialized to 0, they can cause problems in other software which consumes payloads. For example, PAYLOAD_SEGMENT_ENTRY does not use the compression field. If it happens to be a non-existent compression type, the 'cbfstool extract' command fails. BUG=https://ticket.coreboot.org/issues/170 TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86 cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v xxd tianocore.cbfs | head # visually inspect compression field for 0 Change-Id: I359ed117ab4154438bac7172aebf608f7a022552 Signed-off-by: kitching@google.com Reviewed-on: https://review.coreboot.org/27540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18arch/riscv: Fix makefile to only set flags for riscvMartin Roth
This was updating flags for ALL architectures, not just riscv. That was bad, and gave us errors, although they weren't fatal for some reason: i386-elf-gcc: error: missing argument to '-mcmodel=' i386-elf-gcc: error: missing argument to '-march=' i386-elf-gcc: error: missing argument to '-mabi=' This issue started from commit 5fed693a (riscv: add support for modifying compiler options) Add comments to the other 'endif' statements since they're now surrounded by a global ifeq Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/27535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18linux_trampoline: use trampoline RAM for the GDTRonald G. Minnich
The linux trampoline was modifying the existing GDT to add the 0x10 and 0x18 descriptors for Linux. This will not work when the existing GDT is in ROM. Change the code to set up a new GDT in what we know to be RAM. Tested by booting a linux payload. The main reason this works is that Linux almost immediately loads its own GDT and then segment registers. This GDT is a very temporary bridge. Note that none of this change used to be necessary; the coreboot GDT was originally compatible with Linux (ca 2000); then Linux changed. Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/27529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18mb/google/octopus/variants/baseboard: Udpate CPU critical tempSumeet Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with busty workloads like Octane, Aquarium on open yorp board with heat sink, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. With reference to previous APL/reef/coral platforms, this updates 105 degree Celsius for the CPU critical temperature trip value to avoid shutdown. This patch also updates power limit1 value to avoid the abrupt thermal shutdown by DPTF. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 15:18:59 +0000