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2016-04-13superio/smsc/mec1308: Fix AddressMax value for SMBX mailboxMartin Roth
The way this was implemented before was causing ACPI failures. There was also a basic misunderstanding of what the AddressMax field was used for. In this case, because it's a fixed address, it should be the same as the AddressMin field. Getting rid of the addition in the field solves the ACPI output problem. Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-04-13rockchip/common: do not retrieve register pointer twiceVadim Bendebury
The driver interface function derives the driver specific pointer from the API provided handle, no need to use the handle in the local functions. BRANCH=none BUG=none TEST=SPI interface with the flash ROM is still working properly. Change-Id: I7725b658365473c733698ca050e780d1dd5072d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7 Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338090 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13rockchip/rk3288: refactor pwm driverLin Huang
3288 and 3399 use the same pwm controller. With this patch in place it is easy to add support for 3399. BRANCH=none BUG=none TEST=booted veyron_jerry to kernel login prompt Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e Original-Reviewed-on: https://chromium-review.googlesource.com/338019 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3288: refactor i2c interface to allow support of rk3399huang lin
Both SOCs use the same base i2c controller, the difference mostly being the number of interfaces and distribution of the interfaces' registers between register files. Upload check was complaining about misspelled labels, fixed them to pacify the check. With this patch in place it is easy to add support for 3399. BUG=none BRANCH=none TEST=brought up veyron_mickey all the way to booting the kernel. It properly recognized the TPM and the edid of the panel, proving that i2c interface is operational. Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754 Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337971 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3399: Add a stub implementation of the rk3399 SOChuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin board can be booted to Linux login propmt. Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/13915 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13amd/agesa/family12/dimmSpd.c: Indent (tab) fixEdward O'Callaghan
Trivial; Use tab over space for indent. Clean up some ASCII art while here. Change-Id: Id2478d140a98596c5eeefdf5b047c1ca23203909 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/8016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13lenovo/t420: Add new portNicolas Reinecke
This is based on t420s. Tested on a T420 without discrete GPU. There is no support for nvidia gpu and optimus. Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: Iru Cai <mytbk920423@gmail.com> Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8 Reviewed-on: https://review.coreboot.org/11765 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13payloads: add iPXE 'payload' buildMartin Roth
We already have the ability to add a pxe rom to cbfs, but it needs to be configured and built separately. This moves the existing Kconfig options for PXE from device/Kconfig and the top level Makefile.inc to payloads, and adds the option to download and build iPXE as part of the coreboot build process. This configures the serial output of iPXE to match coreboot's serial port configuration by editing the .h files. iPXE doesn't give any real build-time method of setting these configuration options. Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14085 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13util/lint: update lint-000-license-headersMartin Roth
- Add some additional filters for files that do not require license headers. - Add an alternative wording for the BSD license that is used in several files. - Add string for dummy files - Stop checking if there are no files left. - Remove 'local' keyword which is not posix compliant. Change-Id: I2ed1b0572b5fbe84ea86173b7ec2106454399547 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14324 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13romcc: Rewrite the test systemJonathan Neuschäfer
Differences: - The test logic is now only implemented in one place (pending the deletion of the old parts), whereas it previously was implemented both as make rules and as a pair of shell scripts. - Tests don't need to be registered anymore. Just adding a new file with the correct name is enough to have it tested. - The code is hopefully more readable and maintainable. - The new test script supports colors (if the standard output is a terminal and --nocolor was not passed on the command line). Things to do in follow-up patches: - Remove the old test code - Test or remove fail_test*.c, hello_world*.c and raminit_test*.c - Fix regressions that have built up over the years, while making sure not to introduce new ones - Makefile integration - Jenkins integration There are tests in the makefile that specify -fno-always-inline, but this option doesn't exist anymore, so I didn't port them over. Change-Id: Idd6b89368c1e36555cb880c37bbe07035c938cd7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-04-13romcc: Use UNIX line endings in linux testsJonathan Neuschäfer
This makes it easier to check the output against a reference output. Change-Id: I9c7ae538b708399a5cadd18e498618d7480d240f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13romcc: Increase base address in linux ld scriptJonathan Neuschäfer
Newer versions of Linux implement a sysctl variable called vm.mmap_min_addr that controls the minimum address a virtual memory mapping may have[1]. It is usually set to 64KiB. Map the start of the segment specified in util/romcc/tests/ldscript.ld to 128KiB, just to be sure. [1]: https://www.kernel.org/doc/Documentation/sysctl/vm.txt Change-Id: I72a5c65ca5e7d3a77d6ec897ae3287e3ea05cc2f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13southbridge/via: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Id6d11d1cea3ebde4adf63e3d98ac603d85591d5b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13southbridge/ti: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I61938b42c5aa75d1c7706a1c5ae45dace6704c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14330 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13southbridge/ricoh: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I9689bf4ccc5f639bd98d6277bdd27afe4bb4295b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13southbridge/nvidia: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I7a19ed8cf16b9424190800940d2b8ec1a96c5ce9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14328 Reviewed-by: Myles Watson <mylesgw@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13src/soc/marvell: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I4572eec52bf834e4fac7bc5b54ceb591a0173a69 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13src/device: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14325 Reviewed-by: Myles Watson <mylesgw@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13mainboard/google: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13mainboard/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14322 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13device/pci_rom: Always use pci_romPatrick Rudolph
The following series always needs to access the functions provided pci_rom.c. Remove the dependency to CONFIG_VGA_ROM_RUN and depend on CONFIG_PCI instead. Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13intelmetool: Fix detection logic of no MEI deviceDamien Zammit
Previously, on systems that are supposed to have ME but are librebooted, there was no message printed to tell the user that no MEI was detected. Fixed this bug. Change-Id: I59681c194ae5e76533dd777374e26d1aea727337 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14334 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-04-13soc/intel/apollolake: Add tsc_freq.c to all the stagesAndrey Petrov
Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: Enable TPM in bootblock stageBora Guvendik
Configure gpio FST_SPI_CS2_N before verstage so that tpm can be accessed. Change-Id: I238bf1cd508880b686f0625f28175a80de450971 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: Update platform-specific FSP headersAndrey Petrov
This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: Reserve IMRs (Isolated Memory Regions)Andrey Petrov
Certain security features on the platform use IMRs. Unfortunately this memory is unusable for OS or firware. This patch marks IMR regions as unusable. Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: logically group PMC BAR programmingAaron Durbin
The ACPI base address was being programmed sepearately from the other BARs in the PMC device. Group all the programming together so there isn't separate paths for programming the relevant BARs. Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14320 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-13src/soc/intel/common: Fix CID 1295499, remove dead codeLee Leahy
Restructure the nvm_is_write_protected routine to eliminate the dead code error. TEST=Build and run on Kunimitsu Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13lint/lint-stable-004-style-labels: Update scriptMartin Roth
- Look at entire tree instead of just the current commit. This was causing the test to overlook some issues that were already in the tree. - If git is on the system, and the code is in a git repo, use the 'git ls-files' command to find the files to examine. If those conditions aren't met, fall back to using the find command. - Wrap the command so it's easier to read. Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14194 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13MAINTAINERS: add myselfPatrick Rudolph
Add myself to MAINTAINERS file. Change-Id: I959ef193b69095b05ae9e42bd10d3b21001e0bc8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14262 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-04-12crossgcc: skip TARGETARCH for tools that don't use itMartin Roth
Many of the tools and libraries don't use a target architecture, but they were still getting put in one. This change separates out the builds that need the target architecture from the ones that don't, and sets the build directory accordingly. This will help keep from rebuilding the libraries when building all of the tools if you keep the temporary files around (-t option). Change-Id: Id6c17719332f2244657f103f5f07ca7812d51af1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-11sb/amd/sp5100: Apply Sx State Settings per RPR v3.02Timothy Pearson
Change-Id: Iacf84ac7de4362e523ad9d8aa7309eecd5277480 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14308 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02Timothy Pearson
Change-Id: Ifb568ca126283e533232f52175d6147ee500220c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14307 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-04-11sb/amd/sp5100: Disable ASF legacy sensor support per RPR v3.02Timothy Pearson
Change-Id: I8628dc433e12892b0839d727165f609c8b34f66e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11soc/intel/apollolake: Fill _PRT entry in DSDTZhao, Lijian
ACPI aware OS will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC gets fixed interrupt line. Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14243 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/intel/apollolake: Add lpss dsdt entryZhao, Lijian
Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11soc/apollolake/acpi: Fill ACPI HPET tableZhao, Lijian
HPET table is required to report integrated HPET timer to kernel. Without HPET table added,Linux kernel will panic when loading timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13374 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake: Add lpc device driverLance Zhao
A dedicated pci device driver required for LPC devices as the legacy IO range need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver system will have assertion on load RTC DXE driver in UEFI payloads. Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake/acpi: Fill in ACPI MADT tableLance Zhao
ACPI MADT tables required to describe the multiprocessor interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignmentTimothy Pearson
Two of the MCT data structures passed as substructures to ramstage were not packed, and additionally no alignment was specified. On at least SP5100-based platforms, specifying packed with no alignment caused boot failure dependent on the exact compiled binary layout (LPC hang). Specifying the alignment and packing the remaining structures appears to have resolved the remaining LPC hang issues on the KGPE-D16. Note that packing the remaining structures alone was not sufficient to eliminate the hang, however removing the packed attribute entirely (during debugging) did resolve the hang at the expense of potential problems in ramstage. Change-Id: If3a7509ed438870d4d05caaaaa091e1c47bf9b97 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14303 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11soc/intel/apollolake: Enabling using of MRC data when availableAndrey Petrov
Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-11soc/intel/apollolake: Enable CACHE_MRC_SETTINGSHannah Williams
This enables CACHE_MRC_SETTINGS by default as well selects timer configuration. Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14252 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11cpu/x86/tsc: Compile TSC timer for postcar as wellAndrey Petrov
Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11nb/amd/amdfam10: Write MCT variables to flash after PCI configurationTimothy Pearson
The SPI controller needs to be set up on devices such as the SP5100 before it can be accessed to write MCT backup data. Move the backup data write after PCI configuration has been completed. Change-Id: Ibcf31755242ac058407a422ce8aa33d6b0b293c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14305 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake/acpi: Fill ACPI MCFG tableLance Zhao
ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13375 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11util/nvramtool/cli/nvramtool.c: Add newline to error messagePaul Menzel
"CMOS parameter touchpad not found" string needs '\n' termination. Change-Id: Ied431dbc9f94d82e1f4716cfb89ea3d6cf513703 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/6553 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-04-11soc/intel/apollolake: Implement SPI controller driverAlexandru Gagniuc
Implement flash read, write, and erase functionality using the hardware sequencing capabilities of the SOC. Due to changes in hardware requirements, the flash chip must be probed differently than on previous platforms (details explained in comments). Note that this is a minimal implementation, and does not provide all the bells and whistles. Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11cpu/x86/tsc: remove conditional compilationAaron Durbin
The delay_tsc.c compilation unit used the C preprocessor to conditionally compile different code paths. Instead of guarding large blocks of code allow the compiler to optimize out unreachable code. Change-Id: I660c21d6f4099b0d7aefa84b14f1e68d6fd732c3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-11cpu/x86/tsc: compile same code for all stagesAaron Durbin
The delay_tsc.c code took different paths depending __PRE_RAM__ being defined or not. Also, timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment. Clean up the code paths by employing CAR_GLOBAL for the global state which allows the same code to be used in all stages. Lastly, handle apollolake fallout now that init_timer() is not needed in placeholders.c. Change-Id: Ia769fa71e2c9d8b11201a3896d117097f2cb7c56 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14301 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-11cpu/x86/tsc: prepare for CAR_GLOBAL in delay_tsc.cAaron Durbin
The current code in delay_tsc.c uses globals and is heavily guarded by a lot of preprocessor macros. In order to remove __PRE_RAM__ constraints one needs to use CAR_GLOBAL for the global variables. Therefore, abstract away direct access to the globals such that CAR_GLOBAL can be easily employed. Change-Id: I3350d1a762120476926c8d9f5f5a7aba138daf5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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