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2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067xArthur Heymans
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-30riscv: delete src/arch/riscv/prologue.incXiang Wang
This code was copied from x86. It is not needed for RISC-V. Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27544 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30ec/lenovo/h8/acpi: Fix ACPI error in _INIPatrick Rudolph
Store the power on defaults in the _REG method after the ERAM region is ready for use. It might not be ready when accessed from _INI. Tested on Lenovo T430. Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/stout: Use new PMBASE APIPatrick Rudolph
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mb/samsung/lumpy: Use new PMBASE APIPatrick Rudolph
Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/link: Use new PMBASE APIPatrick Rudolph
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30sb/intel/bd82x6x/finalize: Use new PMBASE APIPatrick Rudolph
Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/parrot/smihandler: Use new PMBASE APIPatrick Rudolph
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mb/google/poppy/variants/atlas: Add new Nanya memory optionTim Chen
- add Nanya NT6CL256T32CM-H1 to memory strapping table BUG=b:111906760 BRANCH=none TEST=none Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30mainboard/google/nocturne: simplify camera power referencesMatt Delco
This change primarily moves the PowerResource up to a more common scope so that the _PRx references are simpler. The ^ scope modifier isn't well supported everywhere amongst OSes and drivers. Windows 10 will BSOD early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could not find the object referenced by a _PRx) with the way things are currently laid out). I've also not seen a firmware outside of coreboot that tries to reference count _ON and _OFF. Isn't it up to the OS to deference count, and whatever it tells ACPI is what should happen (i.e., on means on and off means off)? Some of the _UIDs are also duplicated. This change makes them unique. A few cosmetic changes are made so that diffing cam0.asl against cam1.asl has fewer extraneous differences. Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30google/caroline: Change debounce time for jack insertion and ejectionMatt DeVillier
Adapted from chromium commit 7633daa [caroline: Change debounce time for jack insertion and ejection] We are using max debounce time. During this time line, MICBIAS will be zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE) We need to reduce this time to below 100ms for caroline device. BUG=b:79559096 TEST=see there is no more irq before jack insertion/ejection irq complete Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1143109 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27659 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30google/kukui: Enable eMMC in bootblock.Hung-Te Lin
On kukui board, the eMMC is routed to EC for boot ROM emulation when loading bootblock, and should be set back to real eMMC as early as possible after bootblock is loaded. BUG=b:80501386 TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled. BRANCH=None Change-Id: Ifefb2e26ed048c38595907cc0875757410129828 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi
Add 4 helper functions to get microcode info. * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. The simpler thing would be to just move the struct microcode to microcode.h so that the structure members can be dereferenced. To encapsulate the structure details added the helper functions. This information will be used in future to compare microcodes for update. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27365 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30mb/google/poppy/variants/nocturne: enable FPMCU powerNick Vaccaro
Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable ec host event wakeNick Vaccaro
Enable nocturne to wake from lid attach/detach events. BUG=b:111803637 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne wakes from suspend on a lid attach/detach event. Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27649 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/nautilus: Remove obsolete fieldsAlan Chiang
Some fields were only required during early stages of IPU3. Remove some fields that aren't used for the current version of IPU3. BUG:None TEST=Launch camera app and check if it works properly. Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d Signed-off-by: Alan Chiang <alanx.chiang@intel.com> Reviewed-on: https://review.coreboot.org/27617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30mb/cavium/cn8100_sff_evb: Compile devicetree for LinuxPatrick Rudolph
Compile the linux devicetree using dtc and add it to CBFS. Change-Id: I8a98ed7b128f65a6e0109963dbabca91563a315c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/bootblock: Get rid of register X1Patrick Rudolph
The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30mb/google/octopusi/variants/bip: Fix unused pins and those with external ↵Furquan Shaikh
terminations For unused pins, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 TEST=On Bip, flashed image and verified that it boots to OS. Also executed a few suspend resume cycles. Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/27634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30drivers/i2c/da7219: Allow disabling micbias-pulse featureDaniel Kurtz
These two da7219_aad properties are optional: - dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV). [<2800>, <2900>] - dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms) When the Mic Bias Higher Voltage feature is not required, firmware should just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time properties. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:111700809 TEST=On grunt: No "Invalid micbias pulse level" in dmesg Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9 Reviewed-on: https://review.coreboot.org/27613 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30security/tpm: Use unique CBMEM names for TCPA logsPhilipp Deppenwiese
Fix regression introduced in commit f18dc5c7 "Add TCPA logging functionality": Introduced TCPA log got overwritten in acpi.c of x86/arch, due to CBMEM name collision. Use a different cbmem name to have two independent TCPA logs. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30security/vboot: Enable TCPA log extensionPhilipp Deppenwiese
* Implement TCPA log for tspi extend function. * Hook tcpa_log_init into vboot tpm_setup function. * Add TCPA log output for vboot GBB flags and HWID Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
The newly added macros are used for cleaning up the RAM initializatiion code. Change-Id: I3d3782ee1fa524cf69b63ccc7eb73e9a2ace84ec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30northbridge/nehalem: clean up header fileFelix Held
* remove duplicate macro definitions * add brackets to macros Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mainboard/opencellular/rotundu: Add FMAP supportzaolin
* Add 8M and 16M fmap configurations. * Fix kconfig selects. * Add vboot options and fixes Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/25084 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nautilus: Set GPP_D21 to high as defaultSeunghwan Kim
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means LTE tx power is backoff mode as default. We would set GPP_D21 to high to change LTE tx power to normal mode as default. BUG=None BRANCH=poppy TEST=Verified default LTE tx power mode is normal mode as default Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nami: Fix fan is always ONJohn Su
Add the new setting for fan performance state. BUG=b:111860513, b:11865138 TEST=Fan do not run below trip point Change-Id: I894460b8b418217e2477608094c37018437cbb78 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29pnp_device: don't treat missing PNP_MSC devicetree entry as errorFelix Held
Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29device/pnp_device: rewrite pnp_get_ioresourceFelix Held
The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29soc/intel: Remove legacy static TPM asl codePhilipp Deppenwiese
Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27712 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29mb/google/octopus: Perform EC init before bootblock gpio configurationFurquan Shaikh
A variant might talk to the EC to get board id in order to identify the right GPIO configuration. Thus it is important to ensure that the LPC IO windows are configured before this. This change moves the call to perform EC init before configuring bootblock GPIOs. BUG=b:111933657 TEST=Verified that reading board id does not fail on phaser. Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27671 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/opencellular/rotundu: Enable TPM 1.2 supportPhilipp Deppenwiese
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28mainboard/opencellular/rotundu: Add supabrck EMMC supportPhilipp Deppenwiese
Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28sb/intel/bd82x6x: Fix watchdogPatrick Rudolph
* Fix comments * Use defines instead of magic values * Use new PMBASE API to modify registers Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28opencellular/rotundu: Introduce variants for OCPhilipp Deppenwiese
* Add Supabrck v1 variant * Modify rotundu base board Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28util/cbmem: Add cbmem TCPA log supportPhilipp Deppenwiese
* Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28security/tpm: Add TCPA logging functionalityPhilipp Deppenwiese
* TCG spec only applies to BIOS or UEFI. * Therefore implement coreboot TCPA compliant log in CBMEM. * Write CBMEM log into the coreboot table for CBMEM tool access Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 15:46:09 +0000