summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-08-21Boards w/ Winbond superios: Use common config entry codeKeith Hui
Six mainboards with Winbond superios directly configure them in romstage.c. All use the common Winbond romstage code. Change them to use the common config entry code to allow for code refactoring such as [1]. Build tested. [1] https://review.coreboot.org/20988 Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-21mainboard/asrock: add ASRock B75 Pro3-MIru Cai
Tested: - i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2 - debug output from serial port, EHCI debug port not found - Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload - all PCI and PCI Express slots Issues: - sometimes the machine fails to boot, with serial debug output it can be seen it stucks after SMM initialization, and more likely to fail to boot when serial cable is attached - no S3 resume (not tested in vendor firmware) Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-21libpayload: add time()Nicola Corna
Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21ec/lenovo/h8: Add panic methodPatrick Rudolph
Add two additional LED IDs. Add Kconfig menu entries to allow selecting the action to execute on death. Overwrite weak die_notify method to notify user on death. Flash all LEDs and play beep code 10 depending on Kconfig options. Successfully tested on: Tested on Lenovo T500. Tested on Lenovo X200. Tested on Lenovo T430, but only LEDs are flashing. Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Signed-off-by: Patrick Rudolph <siro@das-labor.org Reviewed-on: https://review.coreboot.org/19695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-21google/snappy: Add Raydium touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64821783 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-21google/snappy: Add MELFAS touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize MELFAS touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64779224 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointerPratik Prajapati
Get microcode patch pointer from intel_mp_current_microcode() api of mp_init and change sgx_configure function signature to drop microcode_patch param. Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21009 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21soc/intel/cannonlake: Add support for all UART port indexSubrata Banik
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/skylake: Add support for all UART port indexSubrata Banik
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/cannonlake: Add Kconfig option to select UART indexSubrata Banik
Cannonlake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/skylake: Add Kconfig option to select UART indexSubrata Banik
Skylake/Kabylake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/apollolake: remove duplicate gpio GPE definesAaron Durbin
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present in the common gpio code. Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21intel/common/cpu: Add function to get microcode patch pointerPratik Prajapati
Add mp_current_microcode() function to get the microcode patch pointer. Use this function to avoid reading the microcode patch from the boot media. init_cpus() would initialize microcode_patch global variable to point to microcode patch in boot media and this function can be used to access the pointer. Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/common/smbus: Don't clear random bitsNico Huber
FSP might have done some settings for us there. Use pci_update_config32() since the register is documented to be 32 bits wide. Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21mainboard/google/poppy: Update VR config settingsFurquan Shaikh
Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config settings to match that of soraka. BUG=b:62063434 BRANCH=None TEST=Build and boot poppy. Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21105 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-21mainboard/google/poppy: Remove MPS IMPV8 workaroundFurquan Shaikh
Poppy uses MPS2949 IMVP8 controller and does not need the VR workaround similar to Eve. Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21104 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-20util/inteltool: Fix a comparison between signed and unsigned integersMaciej Suminski
Change-Id: Ic6489c408a87213d3c39626c5379a44acea2c34d Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch> Reviewed-on: https://review.coreboot.org/21024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-20util/me_cleaner: Pull the latest changes from upstreamNicola Corna
Relevant changes (commit 2e8761e): * Add an option to truncate the ME image file * Add full support for Skylake (ME 11) and following, including modules removal, truncation informations and partition relocation * Add two options to generate a shrinked ME image file and the corresponding descriptor with a modified flash layout * Update README.md * Bug fixes Also add a link to the usage guide in the Kconfig help. Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20915 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-08-20payloads/external/GRUB2: Only rebuild on config changesNico Huber
Change-Id: I376eea9a3e02b03010fc5c5a05199ea7b2813220 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-20sb/intel/common: Fix SMBus block commandsArthur Heymans
Clear LAST_BYTE flag at beginning of block commands. For reads, slave device determines in the message format how many bytes it has to transfer out, host firmware only dictates the maximum buffer length. Return SMBUS_ERROR if only partial message was received. For writes, return SMBUS_ERROR if length > 32. For writes, fix off-by-one error reading memory one byte past the buffer end. Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-20nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans
A small typo in the dll setting code prevented this combination from booting. TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2 Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
Moves receive enable calibration to a separate file to lighten raminit.c a bit. Receive enable calibration is quite similar to gm45 so it reuses some of its function names. The functional changes are: * the minimum coarse is now reset for each channel; * on the second fine search for DQS high, TAP overflow is handled by increasing medium; * start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges do the same and the results are more in line with register dumps from vendor bios. These might improve stability. TESTED on ga-g41m-es2l Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-20mb/gigabyte/ga-b75m-d3v: add libgfxinit supportBill XIE
On this device libgfxinit successfully initializes textmode and framebuffer mode on the device connected to the HDMI1 port. VGA port is not tested, due to lack of VGA with valid EDID. Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1. Due to limitations within the libgfxinit's current build system, it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is PCH instead of CPU for which libgfxinit should be configured here. Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-19arch/x86: Sanity checking on HAVE_SMI_HANDLERKyösti Mälkki
Fail at build-time if one of the following happens: Platform includes SMI handler setup function smm_init() in the build when configuration has HAVE_SMI_HANDLER=n. Platform does not implement smm_init_completion() when HAVE_SMI_HANDLER=y. Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-19intel/smm/gen1: Backup default SMM areaKyösti Mälkki
Fix low memory corruption on S3 resume path. Affected platforms were sandy/ivybridge. Change-Id: I7379e7396b61ee4dc2438276d530feffaa1bc8f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21100 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-19i82801dx/gx/ix/jx: Add low-memory backup for S3 pathKyösti Mälkki
SMM relocation code overwrite low memory owned by OS. Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19405 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19arch/x86: Clean up CONFIG_SMP and MAX_CPUS testKyösti Mälkki
Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19arch/x86: Fix ugly NEED_LAPIC useKyösti Mälkki
Change-Id: I2d6fdfd0465fe5f558daa04c6f980f7226596b55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-19soc/intel/skylake: Enable power button SMI when jumping to payloadFurquan Shaikh
Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-18nb/intel/i440bx: Compile debug.c only if CONFIG_DEBUG_RAM_SETUPKeith Hui
... is enabled. Otherwise we are compiling an effectively empty file. Change-Id: I4e3d982066d1fa66a3da5f37e278ec7fd5bb1ea8 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2017-08-18device/smbus: Reuse I2C bus operations where applicableNico Huber
Reuse generic I2C functions that work for SMBus operations as well. Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18drivers/i2c/rx6110sa: Drop I2C interface arbitrationNico Huber
Change-Id: Ib31e77eec639c231520198c0b978d6c3c1eadaed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18Reinvent I2C opsNico Huber
Do not use the global platform_i2c_transfer() function that can only be implemented by a single driver. Instead, make a `struct device` aware transfer() function the only interface function for I2C controller dri- vers to implement. To not force the slave device drivers to be implemented either above generic I2C or specialized SMBus operations, we support SMBus control- lers in the slave device interface too. We start with four simple slave functions: i2c_readb(), i2c_writeb(), i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec- tive SMBus functions. But we keep aliases because it would be weird to force e.g. an I2C EEPROM driver to call smbus_read_byte(). Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18kbc1126_ec_dump: fix some errorsIru Cai
- fix the error caused by signed integer extension - fix fopen mode - one minor style fix Change-Id: Iacc4ea50515ea219bc1868dae0446d576e8dce0c Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/21013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18mainboard/hp: Add HP Elitebook 8460pIru Cai
The code is based on autoport. I'm using a machine with discrete GPU, and gfx.* in devicetree.cb is from 2760p. It can be debug with serial port on dock. Tested: - CPU and memory: i5-2540M, 4G+0 - Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted from vendor UEFI firmware) - USB ports - SD card reader - WLAN - DP display - S3 Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18mainboard/hp: Add HP Elitebook 2570pIru Cai
The code is based on autoport. The EHCI debug port is the upper USB port beside the battery. Tested and working: - CPU and memory: i7-3720QM, 4G+4G - Linux Mint with Linux 4.4 (SeaBIOS payload) - All USB ports - ExpressCard - WLAN - AC and battery status - S3 - Other devices detected: DVD drive, smartcard reader, fingerprint, bluetooth Not tested: - VGA and DP - Ethernet and modem - Dock Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18mainboard/hp: Add HP Elitebook 8470pIru Cai
The code is based on the code generated by autoport. The EHCI debug port is between the DP port and eSATA port. The serial port on dock can also be used for debugging. The model with discrete graphics is not tested. Tested and work: - memory: 0+4G, 4G+0, 4G+4G - Linux (Arch Linux with kernel 4.10.6) boot from SeaBIOS payload with native graphics init - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - AC and battery status (EC) blobs: This laptop uses SMSC KBC1126 EC, and there are two blobs needed by it. You can use the tools in util/kbc1126/ to extract them and insert them to the coreboot image using the following configuration: -> Chipset -> Add firmware images for KBC1126 firmware Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/18985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18mainboard/hp: Add HP Elitebook 2760pIru Cai
The code is generated by autoport. The flash chip is socketed beside the WLAN slot. The EHCI debug port is on right side of the laptop beside the RJ11 connector. Things that work: - memory: 0+8G, 4G+8G - Linux (Linux Mint 18.1 with Linux 4.4) - native graphics init + SeaBIOS payload with SeaVGABIOS - all 3 USB ports - WLAN - WWAN - SD card reader - expresscard - S3 suspend and resume - internal flashing after IFD is unlocked and coreboot is flashed - keyboard, trackpoint and touchpad - fan control - AC and battery status Issues: - Wacom digitizer does not work (even after I add it in DSDT) - GRUB payload will freeze (in all Elitebooks, including chainloading GRUB from SeaBIOS) Things that are not tested: - smart card reader - cable modem (EC) blobs: This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the flash chip. You can use the tools in util/kbc1126 to extract them from OEM firmware, and use the following configuration to insert them to coreboot image: -> Chipset -> Add firmware images for KBC1126 firmware Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/18241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18payload/tianocore: Add patch to preserve coreboot tableArthur Heymans
Credit for this patch goes to 'ReddestDream'. The patch is pulled from https://github.com/MattDevo/edk2 TESTED on thinkpad X200. Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-17soc/intel/common/block: Add functions to common CPU library codeShaunak Saha
This patch adds few helper functions in CPU common libraray code which are mainly needed for ACPI module. The functions those are moved to cpu common code is removed from common acpi files. TEST= System boots properly and no regression observed. Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-17soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao
Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17intel/cannonlake/chip: Add initial PCI enum supportPratik Prajapati
Add callbacks for initial PCI devices enumeration. Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-17intel/common/block/fast_spi: Add config option to disable write statusDuncan Laurie
Chrome OS systems rely on the write status register to enable/disable flash write protection and disabling this opcode breaks the ability to enable or disable write protection with flashrom. Add a configure option for this feature that will disable the opcode for Write Status commands unless CONFIG_CHROMEOS is enabled. Tested to ensure that a default build without CONFIG_CHROMEOS has this option enabled while a build with CONFIG_CHROMEOS does not. Also ensured that when this option is disabled (for Chrome OS) then flashrom can be used with the --wp-enable and --wp-disable commands, depending on the state of the external write protect pin. Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/21021 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-17arch/x86: Make postcar TempRamExit call genericMarshall Dawson
Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-17soc/intel/apollolake: Fix CONFIG_FSP_CAR build errorMarshall Dawson
Remove cpu.h from the cache-as-ram setup and teardown files that rely on the FSP implementation. The struct device statement causes a build failure and there appears to be nothing needed from cpu.h in the two .S files. TEST: Build Google Reef with FSP_CAR selected on Chipset menu and add FSP binaries on the Generic Drivers menu. Change-Id: I560b730c18d7ec73b65f2e195b790e7dcacfd6bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21057 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-17mainboard/google/poppy: Add ACPI objects for NVMEM device GT24C16S and CAT24C16V Sowmya
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16 are the industrial standard electrically erasable programmable read only memory (EEPROM's) and this patch adds ACPI objects and power resources for NVMEM device. Update DOVD method to set sensor IO LDO voltage and remove repetitive code from OVFI, VCMP and NVMP power resources. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Read the NVMEM content via sysfs interface. Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-17soc/intel/skylake: Configure FSP to skip ME MBP stepDuncan Laurie
We do not need or use the Management Engine MBP HOB so that step can be skipped when FSP initializes the ME. BUG=b:64479422 TEST=boot with FSP debug enabled binary and ensure that the output indicates this step is being skipped: Skipping MBP data due to SkipMbpHob set! Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/20951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-17util/lint: Change final-newlines to lint-test from lint-extended-testMartin Roth
The final newline check is taking longer than we'd like to run. Since it runs on every commit as part of the pre-commit check, we want that to run faster than it currently does. Remove LINT_SKIP_NEWLINE_CHECK as it's no longer needed. Change-Id: Ie945dd6caba84e0d23af499d43367d70b1696089 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-17lint: update signed-off-by checkMartin Roth
The current signed-off-by check doesn't really work well as a lint stable test being run by the pre-commit git hook. This test looks at the PREVIOUS commit instead of the staged commit, which works well on the server. In looking for a way to check the staged commit message, I found the commit-msg hook, which is the correct way to check the staged message. - Update the commit message check from a lint-stable test to a lint-extended test. - Add the check for signed-off-by to the commit-msg hook Change-Id: I8be8aef25730d988c7cf1586ae66ecb839d5f756 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 09:09:32 +0000