summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-04-23soc/qualcomm/qcs405: add console.h includePatrick Georgi
Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32422 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23qcs405: Add support of GPIO IRQ APIsTaniya Das
Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23qcs405: clock: Update SPI APITaniya Das
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405. Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23nb/intel/sandybridge: add pch.h includePatrick Georgi
Fixes src/northbridge/intel/sandybridge/raminit_mrc.c:286:3: error: implicit declaration of function 'enable_usb_bar' Change-Id: I48bf59c56b518477a3fc0d75902fc58df6b7def7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32400 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/cannonlake: add missing console.h includePatrick Georgi
Change-Id: Ic23eb57a4096d4301d7f9478d8e65aaeb233de7b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32399 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23cbfstool: Fix cbfs_file_next_attrPatrick Rudolph
The last attribute was never returned. Fix size compare to retrieve all attributes. Manually tested and seen all attributes, including the last one. Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23lib/fmap: Add area read/write functionsT Michael Turney
Change-Id: I7669b8dc07b1aa5f00e7d8d0b1305b3de6c5949c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23linuxboot/Kconfig: Remove symbol name of a `choice`Nico Huber
Kconfig somehow adds spurious booleans for each alternative when the choice itself has a name. That's fixed simply by removing the name. Change-Id: Ic35f0697f1f7bb92c12414c17a8790464b376012 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23coreboot: Run mainboard specific code before Cr50 resetKeith Short
When coreboot checks the TPM and key-ladder state it issues a reboot of the Cr50 with a delay parameter. Older Cr50 code doesn't support the delay parameter and reboots immediately, which prevented coreboot from running the mainboard specific code needed for the AP to come back up. This change calls mainboard_prepare_cr50_reset() prior to sending the VENDOR_CC_IMMEDIATE_RESET command. This change also fixes a false error message from the coreboot log that indicated "Unexpected Cr50 TPM mode 3" when the Cr50 key ladder is disabled. BUG=b:130830178 BRANCH=none TEST=build coreboot on sarien and grunt platforms. TEST=Load Cr50 v3.15, run 'gsctool -a -m disable; reboot'. Verify corebot send the VENDOR_CC_IMMEDIATE_RESET command and that the AP boots normally. Verify event log shows "cr50 Reset Required" TEST=Force Cr50 automatic update. Verify event log shows "cr50 Update Reset". Change-Id: Ib05c9cfde8e87daffd4233114263de5b30822872 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23soc/intel/common/acpi: Add dynamic method around sleepLijian Zhao
Declare plaform level hook method before and after system sleep for possible power management related usage. BUG=N/A TEST=pass with make what-jenkins-does Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie63711748b6dbb99d34910824f2059464543e162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() functionElyes HAOUAS
Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31432 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23configs: Add a target to buildtest the ivybridge mrc.bin bootpathArthur Heymans
Change-Id: Iff15e9586cd3e39850d986582b5943cbb8a184a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23arch/x86/car.ld: Make the vboot tpm log symbols conditionalArthur Heymans
Without VBOOT_MEASURED_BOOT there is no need for these symbols. Change-Id: I96391b7817c79f760713c67bc469164b5514879e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23nb/intel/i945: Check if interleaved even if rank #4 size is zeroElyes HAOUAS
Tested config: Interleaved (config; status before, after): DIMM{0 + 2}: ok, ok DIMM{0 + 3}: Nok, ok DIMM{1 + 2}: ok, ok DIMM{1 + 3}: Nok, ok DIMM{1 + 2 + 3}: ok, ok DIMM{0 + 2 + 3}: ok, ok DIMM{0 + 1 + 2}: ok, ok DIMM{0 + 1 + 3}: Nok, ok Not Interleaved: DIMM{0 + 1 + 3}: Nok, Nok DIMM{0 + 1 + 2}: ok, ok (with single ranked) DIMM{0 + 1 + 2}: Nok, Nok (with only dual ranked) DIMM{0 + 2 + 3}: Nok, ok DIMM{1 + 2 + 3}: ok, ok Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23sb/intel/bd82x6x: fix linking for non-native raminit caseMatt DeVillier
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x] moved early_pch_init() to the southbridge, but failed to include early_pch.c for the non-native raminit case, which now fails to link. As all boards default to native raminit, this was missed by the autobuilder. Adjust early_pch.c to be compiled regardles of ram init type used Test: build/boot google/stout with MRC ram init selected Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23ich7/i945: Use full_reset()Elyes HAOUAS
For full reset, use already defined full_reset() function. Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23sb/intel/lynxpoint: Enable LPC/SIO setup in bootblockArthur Heymans
This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/amd/common: Remove AmdReadEventLog()Kyösti Mälkki
Parameter passing is incorrect here, it should pass complete StdHeader instead of attempting to fill in HeapStatus that should be treated as a field private to AGESA, based on where it is defined in the header files. Furthermore the while() loop did not evaluate the return value. Feature can be brought back at a later date after someone verifies it actually works correctly across different stages. Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/amd/common: Introduce agesa_execute_state()Kyösti Mälkki
Each entrypoint to AGESA goes through the same sequence and have same the function signature. To avoid introducing bunch of preprocessor magic, rename all the agesawrapper_amdXXX() functions that are actual entrypoints to AGESA API, make them static, and provide a single exposed entry function agesa_execute_state(). Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23mb/google/sarein: Add power control for Arcada touchscreenRoy Mingi Park
This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Arcada during S0iX Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23smbios: Add memory type 9 system slot supportLijian Zhao
Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23soc/intel/cannonlake: Enable PlatformDebugConsent by KconfigKane Chen
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. BUG=b:130203864 TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interfaceKane Chen
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug interface of SoC. Ex: USB DBC, DCI debug interface on cnl, whl, cml. Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl codeFrans Hendriks
Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by Intel FSP. Remove ASL code. BUG=N/A TEST=Boot Ubuntu on Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-04-23ACPI: Clarify serial bus revision and specific revisionElyes HAOUAS
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9] are not the same. Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph
Include pch.h in the source files instead in sandybridge.h. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23soc/intel/cannonlake: Add null reference check for Cnvi and XdciAamir Bohra
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23crossgcc: Update acpica to version 20190215Elyes HAOUAS
Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23crossgcc: Update CMake to version 3.14.2Elyes HAOUAS
Release Note : https://cmake.org/cmake/help/v3.14/release/3.14.html "The FindFontconfig module added by 3.14.0 accidentally used uppercase FONTCONFIG_* variable names that do not match our conventions. 3.14.1 revises the module to use Fontconfig_* variable names. This is incompatible with 3.14.0 but since the module is new in the 3.14 series usage should not yet be widespread" Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23crossgcc: Upgrade GCC to version 8.3.0Elyes HAOUAS
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-23sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbaseElyes HAOUAS
Also use macros instead of magic numbers. Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_configArthur Heymans
The pci_or_configx function makes the code shorter and more readable. Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23Klocwork: Fix the Null pointer derefernce found by klocworkThejaswani Putta
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI ↵Robin Broda
devices Signed-off-by: Robin Broda <robin@broda.me> Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payloads/U-Boot: Update to the latest stable 2019.4Arthur Heymans
Change-Id: I4740aa80e3c0faf9b18730390af778abcc92aac3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payload/U-Boot: Fix generating a default config on the master branchArthur Heymans
The name of the default configuration file for x86 coreboot changed. Change-Id: I6544142a70bd3e1e13ee52eccbd5335f8375a4f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payloads/U-Boot: Use a phony target for checking out a revisionArthur Heymans
Change-Id: I5ea4df33545f69c06e4ae2158a1a6c14ead784a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payloads/U-Boot: Unexport the coreboot_exportsArthur Heymans
Without this U-Boot ends up overwriting the coreboot .config when generating a configfile. Change-Id: I62fc0aa3ede0287ffc96915182a2ed5a4877f29d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23mb/google/octopus: Add keyboard backlight support for Droid/BlorbSheng-Liang Pan
Droid/Blorb supports keyboard backlight feature, so enable the ASL code. BUG=b:130330141 BRANCH=octopus TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT. Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23hifive-unleashed: update documentation to match current statePhilipp Hug
Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-22Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"Lijian Zhao
This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22board/kukui: Support ADC value for NCHung-Te Lin
When the components like LCM ID are not installed (i.e., NC), ADC will return some value with much larger variation from standard value (out of the tolerance we set). To support that, we should check tolerance only on non-NC voltages. Also improve the error messages so we can see the ADC raw values instead of simple assertion error (which makes debugging more difficult since we have to build another firmware image just to print the values). BUG=None TEST=Booted on Kukui and got correct SKU ID for NC LCMID. BRANCH=None Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on ArcadaRoy Mingi Park
Currently, Arcada only supports D3hot during S0iX and there is leakage power around 5~10mW depending on SSD vendors. To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2 and two GPIOs are required to be configured. GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to control SSD reset. BUG=b:130741066 TEST=Measure SSD power during S0iX from Arcada(DVT2) Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22arch/x86/car.ld: Also check mrc.bin heap for IvybridgeArthur Heymans
Sandy- and ivybridge use the same mrc.bin that has the heap in an awkward location. Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-21drivers/intel/fsp2_0: Set basename for FSP binariesFelix Singer
Since there is no standardized naming scheme for the FSP binaries, the option USE_FSP_REPO can't be used on some platforms, because some of the filenames differ and the build process awaits "Fsp_*.fd" as filename. As a workaround, add the option -n to SplitFspBin.py, which defines the basename. Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30930 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21nb/intel/haswell: Add an option for where verstage startsArthur Heymans
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 05:32:24 +0000