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2017-10-22superio/ite/common: Add temperature limitsVagiz Trakhanov
Add devicetree options to set temperature limits that are used to alarm user when temperature exceeds defined values. Audio alerts by superio are not implemented yet, but since limits are visible to userland, some software might use them as is. For instance, lm-sensors displays "ALERT" when temperature exceeds limits. Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22superio/ite/common: Add temperature offsetVagiz Trakhanov
Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22soc/intel/cannonlake: Change max root port to 16Lijian Zhao
Cannonlake SOC support up to 16 PCI express root port. BUG=CID 1381813;1381814; Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22soc/intel/skylake: pass SataSpeedLimit param to FSP2Matt DeVillier
The Librem13v2 needs to set this parameter to work around power-related issues with some SATA devices. Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22045 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22purism/librem13v2: Update microcode length in CBFSYouness Alaoui
Microcode blob has been updated, so update the length to match Change-Id: I46ac10e5c6cd6492c98a7034649797f301101abc Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22purism/librem13v2: Fix USB settings and set OC pinYouness Alaoui
The USB settings were wrong in some places, or missing and the USB_OC values were taken from the schematics. Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Update devicetree settingsYouness Alaoui
Disable SataDevSlp and update other values to match vendor/AMI firmware. Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Change DRAM Rcomp/DQS valuesYouness Alaoui
The RComp values have been updated to match what is shown in the schematics. Extracting the Memory configuration blob from the original BIOS (A blob which contains the correct binary sequence matching the RComp values appears in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find and confirm the DQ and DQS mapping. Small code cleaning in romstage.c with no effect. Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22purism/librem13v2: Add reading of serial number from CBFSYouness Alaoui
Check CBFS for 'serial_number' field, and use value if exists; otherwise use value set at compile time. Change-Id: I4b50f6310ca32b9dd372db075a5b5729e3b06619 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22util/ifdtool: Fix region limitation checkYouness Alaoui
Using ifdtool to change layout on a 'ifd v2' file causes an error about region type 5 not being valid. The limit to check against is dynamic depending on ifd version, not static. Change-Id: Id4cdce4eac18fb0d171d1bdfa2044340bf93056a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22intelmetool: Add support for Sunrise Point LPYouness Alaoui
This was tested on Librem 13 v2. Change-Id: I4b56ed8a8a394da2ac5e4bfde6916aa1d39b2654 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22skylake/me: Add debug output of HFST registersYouness Alaoui
The ME status is the interpretation of the status registers, but having the actual status registers printed is important and it doesn't hurt to show them. Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22Update vboot submodule to upstream masterDaisuke Nojiri
Updating from commit id a52fc548 (image_signing: Remove legacy unified build feature) to commit id 3b805725 (tlcl, tpmc: extend GetVersion to report vendor specific data) This brings in 22 new commits. Change-Id: I51e44490e0ffd2c5cc73d439c1f3f8831d816be9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22google/kahlee: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22amd/gardenia: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: I44c7df6a2be149ed61094f67ef1c578736e5b55c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22soc/amd/common: Revert PI blob search hackMarshall Dawson
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and rely on the cbfs search 100% of the time. The change was initially put in to avoid a hang when vboot presearched memory for the blob. The implementation now supports early cbmem init and cbmem_top() is careful to return 0 if DRAM has not yet been set up. As a result the hang no longer occurs and the hack may be removed safely. BUG=b:67747902 Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22src/security: Add security kconfig stubPhilipp Deppenwiese
Change-Id: I965bf87d8673e22c088093f0fa17e93dbb9a00d9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22mb/google/link: Enable libgfxinitNico Huber
Beside the high-resolution eDP panel, it features a dual-mode mini-DP port. Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22soc/amd/stoneyridge: Remove duplicate macros in pci_devs.hChris Ching
BUG=b:68046770 TEST=build Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22intel/i210: Set bus master bit in command registerWerner Zeh
There are still Ethernet drivers out there in the wild which expect that the master enable bit was set by firmware. A missing master enable bit will lead to a non-functional driver. Though it is clear the task of the driver to set this bit it is too late now. So work around this issue on firmware level...again! Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-20kahlee: Set Kahlee GPEsMarc Jones
Add GPE configuration table. Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22). Set the EC and PCIE/WLAN SCI GPIO signals. Set GPE ASL methods for: PCIE/WLAN 8h EHCI 18h XHCI 1fh Note EC GPE3 methods are in the EC ASL. BUG=b:63268311 BRANCH=none TEST=Test lidswitch powers the device on and off at the login screen. Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22096 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20cr50_enable_update: Add printk before EC hibernateShelley Chen
Add printout before EC hibernates during a cr50 update to clarify that failure is due to EC rather than cr50. Ran into a situation where DUT shut down during cr50 update and the EC was the culprit. BUG=None BRANCH=None TEST=None Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22120 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-20google/fizz: Set PL2 value based on sku id/charge max powerShelley Chen
Set PL2 based on either 90% of usb c charger's max power or sku id if using a barrel jack. BUG=b:37473486 BRANCH=None TEST=output debug info for different skus and make sure PL2 set correctly. Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20chromeec: Add function to retrieve usb c charger infoShelley Chen
Add google_chromeec_get_usb_pd_power_info(), which will call the EC_CMD_USB_PD_POWER_INFO host command to retrieve the current and voltage info of the usb c charger. Returns power info in watts. BUG=b:37473486 BRANCH=None TEST=output debug info to make sure that correct power is returned. Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20lib/gpio: constify array inputsAaron Durbin
The arrays of gpio_t are not manipulated in any way within the gpio library. Add const to indicate that. Change-Id: Ie32ab9de967ece22317e2b97b62e85b0757b910d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20stoneyridge: Add SCI/GPE configurationMarc Jones
Add functions for configuring the GPE ACPI SCI events. BUG=b:63268311 BRANCH=none TEST=With the Kahlee GPE setup patch, test lidswitch powers the device on and off at the login screen. Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/stoneyridge: Remove _PRW ASLMarc Jones
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets the GPEs. In addition, Stoney Ridge GPPs don't generate a GPE/SCIs. Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20stoneyridge: Fix USB ASLMarc Jones
Stoney Ridge has one EHCI controller and one XHCI controller. Also, update the Kahlee and Gardenia mainboards ASL to match. Change-Id: I5749ca0640796732e74e551147f8c4446317b77e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20intel/cannonlake_rvp: Update board nameLijian Zhao
Change the board name from cannonlake U DDR4 to U LPDDR4 to match actual platform. TEST=NONE Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20soc/intel/cannonlake: Add platform.aslLijian Zhao
Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20soc/intel/skylake: update GNVS with SGX dataPratik Prajapati
- Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. - With this patch SGX ACPI device would get pached with enumaretd values of ECP device status, base address and length Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/intel/apollolake: update GNVS with SGX dataPratik Prajapati
Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. Change-Id: I692f466d2c6f537d44aa042c4890ee8055c982c8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20intel/common/block/sgx: Add API to enumerate SGX resources and update GNVSPratik Prajapati
Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called to enumerate SGX resources. Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/intel/skylake: Add GNVS variables and include SGX ASLPratik Prajapati
- Add GNVS variables for SGX - Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set - With this patch SGX ACPI device would get created and kernel SGX driver would let loaded Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/intel/apollolake: Add GNVS variables and include SGX ASLPratik Prajapati
- Add GNVS variables for SGX - include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set - With this patch SGX ACPI device would get created and kernel SGX driver would let loaded Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20intel/common/acpi: Add common SGX ASLPratik Prajapati
- Add EPC device for SGX. Kernel SGX driver expects EPC device. - Hid is INT0E0C - version of the object is 1.0, so _STR is "Enclave Page Cache 1.0" Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20vendorcode/amd/pi/00670F00: Remove S3 restore functionsMartin Roth
These functions are not currently used, and were not in the original AGESA source code drop. The structs involved here were marked "private" in AGESA headerfiles and should not be exposed. They could be handled as anonymous structs and required allocation size is communicated by other means. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Iec346205470150257fd9d09131d54231b321740b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-20soc/amd/common: Set AltImageBasePtr to 0Martin Roth
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't set it to VOID. 0 works for either UINT32 or VOID *, as demonstrated by the other 7 places in this file where it's already set to 0 instead of NULL. Change this location to 0 to support either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20Stoney Ridge Platforms: cast AGESA tables to void *Martin Roth
In the original AGESA headers, these tables are not defined as const. Cast them to void * so that they'll work with either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22059 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20Stoney Ridge Platforms: Make AGESA callout tables commonMartin Roth
There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. Move chip specific functions into the stoneyridge directory: - agesa_fch_initreset - agesa_fch_initenv - agesa_ReadSpd Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which to use. Soldered-down memory still needs to be supported in a future commit, as stoney supports both DDR3 & DDR4. A bug has been filed for support for the upcoming Grunt platform. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-20util/genbuild_h: improve robustness against corrupt .git directoriesPatrick Georgi
The new test lets git check if $top is actually a git repo, instead of just looking for clues. BUG=chromium:776174 BRANCH=none TEST=`mv .git .foo; mkdir .git; util/genbuild_h/genbuild_h.sh` provides a valid build.h instead of failing because git is unhappy about the .git directory. Change-Id: I7fcc64d66e0b59fca1479b4c142fd0559aa984f4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20board_status/towiki: Fix link to last report for "clone" boardsJonathan Neuschäfer
I noticed that the "last known good" field for the ThinkPad R400 pointed nowhere. Instead of https://www.coreboot.org/Supported_Motherboards#lenovo.2Ft400 it pointed to https://www.coreboot.org/Supported_Motherboards#lenovo.2Fr400 which does not exist because if a board is marked as a "Clone of" another one in board_info.txt, towiki uses the original board's reports to derive the "last known good" date and color. Change-Id: Ie235ca8e8691f49d041de7c5770eae77cdd444a7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-10-20mainboard/pcengines/apu2: add apu3 and apu5 variantsKamil Wcislo
Apu3 and apu5 are additional variants of apu2 board. Apu3 has no LPC connector exposed, but has additional USB header. It has also 2 slots for SIM cards and one of the gpios is used to control switching between them. Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches). This patch adds support for those other variants by not introducing additional code redundancy. Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Reviewed-on: https://review.coreboot.org/21981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-19soc/amd/stoneyridge: Use macros for PCI_DEVFN callsChris Ching
* Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19soc/amd/stoneyridge: Replace magic registersRichard Spiegel
Replace southbridge registers and register values from magic numbers to literals, provided these registers are currently defined publicly or in NDA datasheet. Registers available only internally to AMD are left unchanged. BUG=b:62199625 Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19Makefile.inc: remove '--global' flag from config check for gitconfig ruleChris Ching
As long as user.name and user.email are set, gitconfig should pass. This handles if values are only set for the local repo, or if values are stored in ~/.config/git/config BUG=none TEST=make gitconfig Change-Id: Ie01e7a155f9e6db35d5991e4303aad85fb277a06 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header file to revision 7.x.15.46. The following item had been updated: 1. Remove/Hide restricted structure. 2. Add EBR as extention of RMT features. 3. Add cpu wakeup timer UPD. 4. Remove XHCI access lock UPD. TEST=NONE Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/intel/cannonlake: Fix HECI error on resetLijian Zhao
Move HECI init from bootblock to romstage, the HECI bar saved by CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage will be read back from PCI. Also add fail safe option to reset in case of HECI command not successful. TEST= Force global reset from FSP and read back HECI bar in debug print. Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik
Avoid calling calculate_dram_base() function to get chipset reserved memory size during pci resource allocation. Rather use EBDA to store chipset reserved memory size while calling cbmem_top_int(). This patch avoids one extra calculate_dram_base() call. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of Intel SoC reserved ranges. Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22099 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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