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This patch sets the GPP_H1 to PAD_CFG_GPO which is general
purpose output with no pullup/down. We need this GPIO for
the detection of soundcard in TGL RVP's.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp successfully. From "aplay -l"
output check that soundcards are listed properly.
Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Update to match the 0.8.6.7B release of PSP blobs.
BUG=b:163857965,b:137123167
TEST=Boot Trembyle, run SST
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update PSP to 0.8.6.7B.
BUG=b:163857965
TEST=none
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I634dadccc51b36f9ac25c3238a794564ce580d5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I080f5b67c6e555fcc025ec11a1d15dddfe3a546d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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To be consistent with the rest of the tree, replace all left ternary
expressions, which are used for device enablement / disablement,
with `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO
Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13
Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0
based, so it doesn't reuse coreboot's stack, but sets up its own stack.
In contrast to all other FSP 2.0 based platforms, this stack isn't in
the CAR region, since AMD Picasso doesn't support CAR and the DRAM is
already available when the x86 cores are released from reset. Selecting
FSP_USES_CB_STACK ended up doing the right thing, but is semantically
wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso
we take the corresponding code path if ENV_CACHE_AS_RAM is false which
is only the case for non-CAR platforms.
BUG=b:155501050
TEST=Timeless build results in an identical binary for amd/mandolin,
asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases
here.
Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add CPUID for CPX-SP A1 (also called QS) processor.
DeltaLake DVT server uses CPX-SP A1 processor.
TESTED=booted DeltaLake DVT server to target OS.
[root@localhost ~]# dmidecode -t 1
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes
System Information
Manufacturer: Wiwynn
Product Name: Delta Lake DVT
Version: YoDL03
Serial Number: BZA02200122N01A
UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF
Wake-up Type: Reserved
SKU Number: Not Specified
Family: DeltaLake
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update dq/dqs mappings based on halvor schematics.
BUG=b:162892573
BRANCH=none
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Then boot Halvor successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Configure gpio settings for enabling card reader function.
BUG=b:153680359
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that the sd card is mount on /dev/mmcblk0 successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44169
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add driver for MT8192 SPI controller
TEST=Boots correctly on MT8192EVB
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This reduces the differences between both ME source code files.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I08e07ca2691bb854682692476153a98967bf05da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob
into FW_MAIN_X partitions.
BUG=b:145796136
Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates regions-for-file function in the
security/vboot/Makefile.inc to support adding a CBFS file into
required FMAP REGIONs in a flexible manner. The file that needs to be
added to specific REGIONs, those regions list should be specified in the
regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable.
For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT,
then below code needs to be added in a Makefile.inc.
regions-for-file-foo := FW_MAIN_B,COREBOOT
cbfs-file-y := foo
foo-file := foo.bin
foo-type := raw
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The first Makefile to support building minimal stage files for MT8192 SOC.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add minimal function to report SDRAM size.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43961
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO
to 8MiB") updated the flash layout which moved RW_SECTION_A and
RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION
and PICASSO_FW_B_POSITION configs need to be updated accordingly to
retain the same behavior as before i.e. amdfw_a/b are placed at the
start of FW_MAIN_A/B by placing them right after the CBFS header.
This change fixes the value of PICASSO_FW_A_POSITION and
PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS.
BUG=b:161949925
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Starting with v3.6 of reference schematics, headphone jack interrupt
is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no
longer need I2S wake to be enabled in the ACP for boards using v3.6+
version of schematics.
This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default
0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl()
if the board is still using older version of reference schematics.
BUG=b:159934887
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Latest EDK2 code inside
"UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c"
is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence
coreboot need to fill required information (package, core and thread
count).
TEST=Able to see package, core and thread information as part of FSP
debug log.
Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Update FSP headers for Tiger Lake platform generated based FSP
version 3313. Previous version was 3274.
Changes Include:
1. Update comments
2. Fix comment typos
3. UPD offset updates
BUG=b:163582213
BRANCH=none
TEST=build and boot volteer proto2
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2784c5b7c8f71c1355c1c36a27cc88080c7c2647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure gpio/overridetree settings for WiFi/BT functions.
Then WiFi/BT functions are enabled on Halvor.
BUG=b:153680359, b:163004808
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that WiFi/BT can scan devices successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In CB:43701 the trembyle touchscreen parameters were not updated
to expose the stop gpio properly.
BUG=b:162973325
Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.
BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia
system. Add information on sensors, power limits and tcc_offset for DTT
based thermal control.
BRANCH=None
BUG=b:161993459
TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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espi_poll_status describes better what the function actually does, since
it polls the status register instead of just doing a single read to
check.
Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It's not needed anywhere else.
Change-Id: Ibc02e432bbc669b3fcfcb8add3c7b0c2a9f77d77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44339
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41946
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the ranges of bitfields as comments on the struct.
Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: I30cdca0240afced2949639193caa2f11aca1c60d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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Also remove the meaningless `sata_traffic_monitor` devicetree option.
Function parameters will be removed in a reproducible follow-up.
Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There's no mobile ICH10 variant. This was copied from i82801ix.
Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Taken directly from i82801jx code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ia37c5feb5a61793c10496a2d9cabb7661aa758b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These were probably copy-pasted from some ICHx southbridge, and then
some were corrected because native PCH init uses them. Delete the
definitions which are unused and are invalid for this southbridge.
Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These were probably copy-pasted from some ICHx southbridge. However,
datasheet shows that some of these are located elsewhere, and some
others have disappeared completely. As they aren't in use, drop them.
Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
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This device doesn't exist on these southbridges.
Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Create the lindar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.2).
BUG=b:161089195
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_LINDAR
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: I08923cde932b7304bcb01cd747530c87949e4692
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.
BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.
Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On CNP-H, only four I2C controllers are available, so PCI devices 19.0
and 19.1 are missing. However, PCI device 19.2 still exists as UART 2.
That function 0 is missing means UART 2 can only be used in ACPI mode.
Both devices need to be marked as hidden on the devicetree so that the
allocator takes UART 2 into account.
Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "ACPI mode".
Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reorganizes flash map layout for zork to allow WP_RO to
grow to 8MiB. This is to allow more space for the firmware UI screens
in RO. Following changes are made in the layout:
1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for
MRC cache. Next section can start on 64K boundary immediately after
MRC cache.
2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB
each. Each region is currently at ~2MiB of usage.
3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size
supported by coreboot.
4. SMMSTORE is restricted to 4K.
5. RW_LEGACY region is dropped down to ~1.9MiB.
BUG=b:161949925
TEST=Verified that write-protection for RO still works fine, device
boots in recovery and non-recovery mode. Also, verified that the dump
of fmap looks correct:
dump_fmap -h firmware/image-trembyle.serial.bin
name start end size
WP_RO 00800000 01000000 00800000
RO_SECTION 00804000 01000000 007fc000
COREBOOT 00875000 01000000 0078b000
GBB 00805000 00875000 00070000
RO_FRID 00804800 00804840 00000040
FMAP 00804000 00804800 00000800
RO_VPD 00800000 00804000 00004000
RW_LEGACY 0061d000 00800000 001e3000
SMMSTORE 0061c000 0061d000 00001000
RW_NVRAM 00617000 0061c000 00005000
RW_VPD 00615000 00617000 00002000
RW_SHARED 00611000 00615000 00004000
VBLOCK_DEV 00613000 00615000 00002000
SHARED_DATA 00611000 00613000 00002000
RW_ELOG 00610000 00611000 00001000
RW_SECTION_B 00310000 00610000 00300000
RW_FWID_B 0060ff00 00610000 00000100
FW_MAIN_B 00312000 0060ff00 002fdf00
VBLOCK_B 00310000 00312000 00002000
RW_SECTION_A 00010000 00310000 00300000
RW_FWID_A 0030ff00 00310000 00000100
FW_MAIN_A 00012000 0030ff00 002fdf00
VBLOCK_A 00010000 00012000 00002000
RW_MRC_CACHE 00000000 00010000 00010000
SI_BIOS 00000000 01000000 01000000
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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In order to help identifying right DRAM info (especially in user space),
we want to unify the mapping table and do the device-specific mapping by
a virtual offset based on build config.
BUG=b:161768221,b:159301679
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add PLL and clock init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add MT8192 GPIO driver.
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43959
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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