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2013-03-21rmodule: add ability to calculate module placementAaron Durbin
There is a need to calculate the proper placement for an rmodule in memory. e.g. loading a compressed rmodule from flash into ram can be an issue. Determining the placement is hard since the header is not readable until it is decompressed so choosing the wrong location may require a memmove() after decompression. This patch provides a function to perform this calculation by finding region below a given address while making an assumption on the size of the rmodule header.. Change-Id: I2703438f58ae847ed6e80b58063ff820fbcfcbc0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2788 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21armv7: add function for dcache_clean_by_mva()David Hendricks
This adds a function for using the DCCMVAC instruction (dcache clean by MVA at point of coherency (main memory)). We already have the inline defined, it's just not used by anything. Change-Id: Ia0641566a8881335bed8da2963e1db8321d74267 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2871 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: add a helper function for dcache ops by MVADavid Hendricks
This adds a helper function for dcache ops by MVA which will perform the specified operation on a given memory range. This will make it more trivial to add other data cache maintenance routines. Change-Id: I01d746d5fd2f4138257ca9cab9e9d738e73f8633 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: cosmetic changes to new cache codeDavid Hendricks
This clarifies and/or fixes formatting of some comments and alphabetizes some function prototypes and inlines. It also corrects references to "modified virtual address" (MVA). Change-Id: Ibcdda4febf915cc4a1996a5bbb4ffecbcb50a324 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2869 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: remove old isb() and dsb() macrosDavid Hendricks
This removes some old macros that we no longer use. Change-Id: I9d87beb5c2deca228cdf89a98e54b2779be0f0ea Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2868 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: move armv7_invalidate_caches() to cache.cDavid Hendricks
This just moves cache maintenance stuff from the armv7 bootblock code to cache.c Change-Id: I0b3ab58a1d8a3fe3d9568e02e156a36b6f33ca0b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2867 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-20x86: don't clear bss in ramstage entryAaron Durbin
The cbfs stage loading routine already zeros out the full memory region that a stage will be loaded. Therefore, it is unnecessary to to clear the bss again after once ramstage starts. Change-Id: Icc7021329dbf59bef948a41606f56746f21b507f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2865 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20f15tn/Include/OptionIdsInstall.h: Remove idle `… || )`Siyuan Wang
Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2864 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-20ARM: remove assembly code dump when stages.o is builtRonald G. Minnich
For diagnostic purposes we had been dumping the assembly code when stages.o was built. We've past the need to do this and it's confusing to watch. Change-Id: Ib84cb73ed9dad3454efcb2be90d990ce88575229 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2555 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-20ARM: Fix the ldscripts so that exit/enter stage work correctly.Ronald G. Minnich
Remove the spurious creation of a start symbol, and use the stage_entry symbol directly. Change-Id: Ia62d5c056ac8b20c8ffdb78bff3d306065b6c45f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2560 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-20Supermicro H8SCM: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the h8scm mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I575221039ad65a59ae0f93397ef1038b669e81c7 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20AMD Dinar: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the dinar mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() were created from code that was removed from AmdMemoryReadSPD() in dimmSpd.c. The functionality is specific to the dinar mainboard configuration and was therefore split from the generic read SPD functionality. Change-Id: I1e4b9a20dc497c15dbde6d89865bd5ee7501cdc0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20Tyan S8226: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the s8226 mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() started by duplicating sp5100_set_gpio() and sp5100_restore_gpio(), which were in dimmSpd.c. In addition to renaming the functions to more specifically state their purpose, some cleanup and magic number reduction was done. Change-Id: I1eaf64986ef4fa3f89aed2b69d3f9c8c913f726f Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2827 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20Supermicro H8QGI: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the h8qgi mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() started by duplicating sp5100_set_gpio() and sp5100_restore_gpio(), which were in dimmSpd.c. In addition to renaming the functions to more specifically state their purpose, some cleanup and magic number reduction was done. Change-Id: I346ebd8399d4ba3e280576e667fdc62fa75a63b8 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20cbfstool locate: Implement alignment switch --align/-aHung-Te Lin
cbfstool usage change: "-a" for "cbfstool locate" can specify base address alignment. To support putting a blob in aligned location (ex, microcode needs to be aligned in 0x10), alignment (-a) is implemented into "locate" command. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 Also verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I78b549fe6097ce5cb6162b09f064853827069637 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2824 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-20link/graphics: Add support for EDIDRonald G. Minnich
This code is taken from an EDID reader written at Red Hat. The key function is int decode_edid(unsigned char *edid, int size, struct edid *out) Which takes a pointer to an EDID blob, and a size, and decodes it into a machine-independent format in out, which may be used for driving chipsets. The EDID blob might come for IO, or a compiled-in EDID BLOB, or CBFS. Also included are the changes needed to use the EDID code on Link. Change-Id: I66b275b8ed28fd77cfa5978bdec1eeef9e9425f1 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20link/graphics: New state machineRonald G. Minnich
This is a new state machine. It is more programmatic, in the case of auxio, and has much more symbolic naming, and very few "magic" numbers, except in the case of undocumented settings. As before, the 'pre-computed' IO ops are encoded in the iodefs table. A function, run, is passed and index into the table and runs the ops. A new operator, I, has been added. When the I operator is hit, run() returns the index of the next operator in the table. The i915lightup function runs the table. All the AUX channel ops have been removed from the table, however, and are now called as functions, using the previously committed auxio function. The iodefs table has been grouped into blocks of ops, which end in an I operator. As the lightup function progresses through startup, and the run() returns, the lightup function performs aux channel operations. This code is symbolic enough, I hope, that it will make haswell graphics bringup simpler. i915io.c, and the core of the code in i915lightup.c, were programatically generated, starting with IO logs from the DRM startup code in the kernel. It is possible to apply the tools that do this generation to newer IO logs from the kernel. Change-Id: I8a8e121dc0d9674f0c6a866343b28e179a1e3d8a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20link/graphics: implement a palette setting operatorRonald G. Minnich
Add a new operator, P, for the state machine, meaning implement a palette fill. Implement a function (palette) that fills the palette when the P operator is hit. This replaces 256 lines in the state machine table with 1. Change-Id: I67d9219fe7de0ecf1fb9faf92130c00c9f5f8e88 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20x86: provide more C standard environmentAaron Durbin
There are some external libraries that are built within coreboot's environment that expect a more common C standard environment. That includes things like inttypes.h and UINTx_MAX macros. This provides the minimal amount of #defines and files to build vboot_reference. Change-Id: I95b1f38368747af7b63eaca3650239bb8119bb13 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2859 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20haswell: drop memory reservation for sandybridge GPU bugDuncan Laurie
This is not needed in haswell. Change-Id: I23817c2e01be33855f9d5a5e389e8ccb7954c0e2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2847 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20Intel: Update CPU microcode for Sandybridge/Ivybridge CPUsStefan Reinauer
Using the CPU microcode update script and Intel's Linux* Processor Microcode Data File from 2013-02-22 Change-Id: I853e381240b539b204c653404ca3d46369109219 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2846 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20Intel: Update CPU microcode for 1067x CPUsStefan Reinauer
Using the CPU microcode update script and Intel's Linux* Processor Microcode Data File from 2013-02-22 Change-Id: I4585288905cf7374e671894ab37f125220ae535e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2843 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19link/graphics: add functions to support aux channel communicationsRonald G. Minnich
For full integration of FUI into coreboot, we need aux channel communcations. The intel_dp.c is a file taken from Linux and is used for aux channel comms. This file has been cut down to work with coreboot. For now it is associated with the link mainboard until we get a better handle on how this all fits together. This code is almost certainly usable on other platforms in the long term. But one step at a time. Change-Id: I7be4c56e0a7903f3901ac86e12b28f3bdc0f7947 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19armv7/exynos/snow: new cache maintenance APIDavid Hendricks
This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19rmodule: add ramstage supportAaron Durbin
Coreboot's ramstage defines certain sections/symbols in its fixed static linker script. It uses these sections/symbols for locating the drivers as well as its own program information. Add these sections and symbols to the rmodule linker script so that ramstage can be linked as an rmodule. These sections and symbols are a noop for other rmodule-linked programs, but they are vital to the ramstage. Also add a comment in coreboot_ram.ld to mirror any changes made there to the rmodule linker script. Change-Id: Ib9885a00e987aef0ee1ae34f1d73066e15bca9b1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2786 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19google/snow: fix a GPIO array indexDavid Hendricks
This fixes a trivial error with the recovery mode GPIO index. Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19lynxpoint: Add cbfs_load_payload() implementationAaron Durbin
SPI accesses can be slow depending on the setup and the access pattern. The current SPI hardware setup to cache and prefetch. The alternative cbfs_load_payload() function takes advantage of the caching in the CPU because the ROM is cached as write protected as well as the SPI's hardware's caching/prefetching implementation. The CPU will fetch consecutive aligned cachelines which will hit the ROM as cacheline-aligned addresses. Once the payload is mirrored into RAM the segment loading can take place by reading RAM instead of ROM. With the alternative cbfs_load_payload() the boot time on a baskingridge board saves ~100ms. This savings is observed using cbmem.py after performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries. This is booting with a depthcharge payload whose payload file fits within the SMM_DEFAULT_SIZE (0x10000 bytes). Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries: Baseline Alt -------- -------- 90:3,859,310 (473) 90:3,863,647 (454) 99:3,989,578 (130,268) 99:3,888,709 (25,062) 90:3,899,450 (477) 90:3,860,926 (463) 99:4,029,459 (130,008) 99:3,890,583 (29,657) 90:3,834,600 (466) 90:3,890,564 (465) 99:3,964,535 (129,934) 99:3,920,213 (29,649) Booted baskingridge many times and observed 100ms reduction in TS_SELFBOOT_JUMP times (time to load payload). Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19x86: remove stack definition in linker scriptAaron Durbin
In order to prepare the ramstage to be linked by the rmodule linker the stack needs to be self-contained within the ramstage objects. The reasoning is that the rmodule linker provides a way to define a heap, but it doesn't currently have a region for the stack. The downside to this is that memory footprint of the ramstage can change when compared before this change. The size difference stems from the link ordering of the objects as the stack is now defined within c_start.S. The size fluctuation ranges from 0 to CONFIG_STACK_SIZE - 1 because of the previous behavior or aligning to CONFIG_STACK_SIZE. It should be noted that such an alignment is unnecessary for 32-bit x86 as the alignment requirement for the stacks are 4 byte alignment. Also the memory footprint is still dominated by CONFIG_RAMTOP and CONFIG_RAMBASE. Change-Id: I63a4ddd249104bc27aff2ab6b39fc6db12b54028 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2785 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19cbfs: alternative support for cbfs_load_payload()Aaron Durbin
In certain situations boot speed can be increased by providing an alternative implementation to cbfs_load_payload(). The ALT_CBFS_LOAD_PAYLOAD option allows for the mainboard or chipset to provide its own implementation. Booted baskingridge board with alternative and regular cbfs_load_payload(). Change-Id: I547ac9881a82bacbdb3bbdf38088dfcc22fd0c2c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2782 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19bd82x6x: Fix compiling with USB debug port supportRonald G. Minnich
At some point, compiles with USB Debug port stopped working. This change makes a trivial reordering in the code and adds two makefile entries to make it build without errors. It also works on stout. Build and boot as normal. Works. Enable CONFIG_USB, connect USB debug hardware to the correct port (on stout, that's the one on the left nearest the back) and watch for output. Change-Id: I7fbb7983a19b0872e2d9e4248db8949e72beaaa0 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2784 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19AMD Fam15: Add SPD read functions to wrapper codeKimarie Hoot
Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBus initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2777 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19cbfstool locate: Rename -a align switch to -P for page sizeHung-Te Lin
cbfstool usage change: The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size". The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000 # output: 0x44, which does not look like aligned to 0x40000. To prevent confusion, it's now switched to "-P/--page-size". Verified by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 Reviewed-on: http://review.coreboot.org/2730 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-19Include byteorder.h for the definition of ntohl in romstage.cHung-Te Lin
A fix to eliminate warnings when building romstage files with ChromeOS compilers Change-Id: Ia5d7bbdde3aa3439fd493f5795f2cc2bf4c4c187 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19haswell: wait 10ms after INIT IPIAaron Durbin
There should be a fixed 10ms wait after sending an INIT IPI. The previous implementation was just waiting up to 10ms for the IPI to complete the send. That is not correct. The 10ms is unconditional according to the documentation. No ill effects were observed with the previous behavior, but it's important to follow the documentation. Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2780 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19haswell: Parallel AP bringupAaron Durbin
This patch parallelizes the AP startup for Haswell-based devices. It does not touch the generic secondary startup code. Instead it provides its own MP support matching up with the Haswell BWG. It seemed to be too much trouble to support the old startup way and this new way. Because of that parallel loading is the only thing supported. A couple of things to note: 1. Micrcode needs to be loaded twice. Once before MTRR and caching is enabled. And a second time after SMM relocation. 2. The sipi_vector is entirely self-contained. Once it is loaded and written back to RAM the APs do not access memory outside of the sipi_vector load location until a sync up in ramstage. 3. SMM relocation is kicked off by an IPI to self w/ SMI set as the destination mode. The following are timings from cbmem with dev mode disabled and recovery mode enabled to boot directly into the kernel. This was done on the baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The kernel has console enabled on the serial port. Entry 70 is the device initialization, and that is where the APs are brought up. With these two examples it looks to shave off ~200 ms of boot time. Before: 1:55,382 2:57,606 (2,223) 3:3,108,983 (3,051,377) 4:3,110,084 (1,101) 8:3,113,109 (3,024) 9:3,156,694 (43,585) 10:3,156,815 (120) 30:3,157,110 (295) 40:3,158,180 (1,069) 50:3,160,157 (1,977) 60:3,160,366 (208) 70:4,221,044 (1,060,677) 75:4,221,062 (18) 80:4,227,185 (6,122) 90:4,227,669 (484) 99:4,265,596 (37,927) 1000:4,267,822 (2,225) 1001:4,268,507 (685) 1002:4,268,780 (272) 1003:4,398,676 (129,896) 1004:4,398,979 (303) 1100:7,477,601 (3,078,621) 1101:7,480,210 (2,608) After: 1:49,518 2:51,778 (2,259) 3:3,081,186 (3,029,407) 4:3,082,252 (1,066) 8:3,085,137 (2,884) 9:3,130,339 (45,202) 10:3,130,518 (178) 30:3,130,544 (26) 40:3,131,125 (580) 50:3,133,023 (1,897) 60:3,133,278 (255) 70:4,009,259 (875,980) 75:4,009,273 (13) 80:4,015,947 (6,674) 90:4,016,430 (482) 99:4,056,265 (39,835) 1000:4,058,492 (2,226) 1001:4,059,176 (684) 1002:4,059,450 (273) 1003:4,189,333 (129,883) 1004:4,189,770 (436) 1100:7,262,358 (3,072,588) 1101:7,263,926 (1,567) Booted the baskingridge board as noted above. Also analyzed serial messages with pcserial enabled. Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19intel microcode: split up microcode loading stagesAaron Durbin
This patch only applies to CONFIG_MICROCODE_IN_CBFS. The intel microcode update routine would always walk the CBFS for the microcode file. Then it would loop through the whole file looking for a match then load the microcode. This process was maintained for intel_update_microcode_from_cbfs(), however 2 new functions were exported: 1. const void *intel_microcode_find(void) 2. void intel_microcode_load_unlocked(const void *microcode_patch) The first locates a matching microcode while the second loads that mircocode. These new functions can then be used to cache the found microcode blob w/o having to re-walk the CBFS. Booted baskingridge board to Linux and noted that all microcode revisions match on all the CPUs. Change-Id: Ifde3f3e5c100911c4f984dd56d36664a8acdf7d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19AMD Dinar: Remove Unused Oem.h Header FileKimarie Hoot
Having this header file in the mainboard directory breaks the dinar build on cygwin because the header file in the dinar mainboard is used instead of the correct header file src/vendorcode/amd/cimx/sb700/OEM.h. The build probably works fine on Linux systems because, due to case-sensitivity, Oem.h will not match the #include "OEM.h" statement in src/southbridge/amd/cimx/sb700/Platform.h. The Oem.h file in the dinar mainboard is not used by any other source files, and the defines in the dinar mainboard are duplicated by defines in the correct OEM.h file. Therefore, the file can be safely removed. Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2776 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-18SMM: link against libgccStefan Reinauer
The non-relocatable SMM code was changed to link against libgcc a while back so that printk could use built-in division instead of a hand crafted div() function. However, the relocatable SMM code was not adapted by mistake. This patch links the relocatable SMM against libgcc, too, so we can enable it for Haswell. Change-Id: Ia64a78e2e62348d115ae4ded52d1a02c74c5cea4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2727 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: add romstage_after_car() functionAaron Durbin
There are changes coming to perform more complex tasks after cache-as-ram has been torn down but before ramstage is loaded. Therefore, add the romstage_after_car() function to call after cache-as-ram is torn down. Its responsibility is for loading the ramstage and any other complex tasks. For example, the saving of OS-controlled memory in the resume path has now been moved into C instead of assembly. Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: move call site of save_mrc_data()Aaron Durbin
The save_mrc_data() was previously called conditionally in the raminit code. The save_mrc_data() function was called in the non-S3 wake paths. However, the common romstage_common() code was checking cbmem initialization things on s3 wake. Between the two callers cbmem_initialize() was being called twice in the non-s3 wake paths. Moreover, saving of the mrc data was not allowed when CONFIG_EARLY_CBMEM_INIT wasn't enabled. Therefore, move the save_mrc_data() to romstage_common. It already has the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT requirement from save_mrc_data() as well as the call to cbmem_initialize(). Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2756 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: romstage: pass stack pointer and MTRRsAaron Durbin
Instead of hard coding the policy for the stack and MTRR values after the cache-as-ram is torn down, allow for the C code to pass those policies back to the cache-as-ram assembly file. That way, ramstage relocation can use a different stack as well as different MTRR policies. Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: unify romstage logicAaron Durbin
This commit pulls in all the common logic for romstage into the Haswell cpu directory. The bits specific to the mainboard still reside under their respective directories. The calling sequence bounces from the cpu directory to mainboard then back to the cpu directory. The reasoning is that Haswell systems use cache-as-ram for backing memory in romstage. The stack is used to allocate structures. However, now changes can be made to the romstage for Haswell and apply to all boards. Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: remove unused sys_info structureAaron Durbin
This structure is not used nor the variable being instantiated on the stack. Remove them. Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2753 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: adjust CAR usageAaron Durbin
It was found that the Haswell reference code was smashing through the stack into the reference code's heap implementation. The reason for this is because our current CAR allocation is too small. Moreover there are quite a few things to coordinate between 2 code bases to get correct. This commit separates the CAR into 2 parts: 1. MRC CAR usage. 2. Coreboot CAR usage. Pointers from one region can be passed between the 2 modules, but one should not be able to affect the others as checking has been put into place in both modules. The CAR size has effectively been doubled from 0x20000 (128 KiB) to 0x40000 (256KiB). Not all of that increase was needed, but enforcing a power of 2 size only utilizes 1 MTRR. Old CAR layout with a single contiguous stack with the region starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | MRC global variables | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ | ROM stage stack | | | | | +---------------------------------------+ | MRC Heap 30000 bytes | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 There was some hard coded offsets in the reference code wrapper to start the heap past the console buffer. Even with this commit the console can smash into the following region depending on what size CONFIG_CONSOLE_CAR_BUFFER_SIZE is. As noted above This change splits the CAR region into 2 parts starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ | MRC Region | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | ROM stage stack | | | | | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE, which represents the expected stack usage for the romstage. A marker is checked at the base of the stack to determine if either the stack was smashed or the console encroached on the stack. Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18rmodule: add rmodules class and new typeAaron Durbin
Add an rmodules class so that there are default rules for compiling files that will be linked by the rmodule linker. Also, add a new type for SIPI vectors. Change-Id: Ided9e15577b34aff34dc23e5e16791c607caf399 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2751 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18wtm2: Disable USB port 7 (SD card) due to hangDuncan Laurie
This is causing a hang in depthcharge. For now just disable this port. Change-Id: I87a6db2d8361588e82eee640c74cea690115bed5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18libpayload: Fix the config file dependency in the Makefile templateGabe Black
The template had a dependency on config.h which was correct for coreboot, where this build system originally came from, but not for libpayload which uses the differently named libpayload-config.h, presumably to avoid colliding with a config.h used by the actual payload. Because libpayload-config.h is now effectively a dependency of everything, it doesn't have to be added piecemeal in Makefile.inc. Change-Id: I01f20d363cb1393fa1cdcf0dc916670db90294e9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18libpayload: Make keycode constants available outside of curses.h.Gabe Black
And include the new, split out version in drivers/keyboard.c and drivers/usb/usbhid.c. Those files were including curses.h just for those definitions, but the include path was only fixed up to to point to the libpayload versions of those files if one of the variants of curses was compiled in. If neither was, gcc would fall back to the system version of that header which is wrong. Change-Id: I8c2ee0baf5f0702bd8c713c8dd4613a4bb269ce5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2762 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18rmodule: include heap in bss sectionAaron Durbin
By including the heap in the bss output section the size is accounted for in a elf PT_LOAD segment. Without this change the heap wasn't being put into a PT_LOAD segment. The result is a nop w.r.t. functionality, but readelf and company will have proper MemSiz fields. Change-Id: Ibfe9bb87603dcd4c5ff1c57c6af910bbba96b02b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2750 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18rmodule: add 16 bytes of paddingAaron Durbin
There is a plan to utlize rmodules for loading ramstage as a relocatable module. However, the rmodule header may change. In order to provide some wiggle room for changing the contents of the rmodule header add some padding. This won't stop the need for coordinating properly between the romstage loader that may be in readonly flash and rmodule header fields. But it will provide for a way to make certain assumptions about alignment of the rmodule's program when the rmodule is compressed in the flash. Change-Id: I9ac5cf495c0bce494e7eaa3bd2f2bd39889b4c52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2749 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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